Micronetwork-based integration for SOCs

Wingard, Drew

doi:10.1145/378239.379046

Cited by 98 publications

(26 citation statements)

References 4 publications

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“…Non-scalability of these approaches was discussed in [1], [6], [9]. However, modern on-chip buses have evolved to multi-layered and segmented structures, supporting split transactions, burst transfers and parallel operations [12]- [14]. From several aspects they can be considered as networks but still, they don't provide effective spatial reuse of resources and do not utilize packet or wormhole switching associated with distributed routing and congestion/flow control.…”

Section: Abstract-we Define Quality Of Service (Qos) and Cost Model Fmentioning

confidence: 99%

QNoC: QoS architecture and design process for network on chip

Bolotin

Cidon

Ginosar

et al. 2004

Journal of Systems Architecture

451

295

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Section: Abstract-we Define Quality Of Service (Qos) and Cost Model Fmentioning

confidence: 99%

QNoC: QoS architecture and design process for network on chip

Bolotin

Cidon

Ginosar

et al. 2004

Journal of Systems Architecture

451

295

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“…Reserved slots traverse the network in a well synchronised manner without having to arbitrate for the output link with the rest of the traffic. The Aethereal NoC developed at Philips and the Sonics on-chip bus employ a TDM technique to support guaranteed throughput [34,35]. Although TDM provides a high level of QoS it is unsuitable for asynchronous implementation because it requires global synchronisation between network elements.…”

Section: Qos For Nocsmentioning

confidence: 99%

Asynchronous on-chip networks

Amde¹,

Felicijan²,

Efthymiou³

et al. 2006

System-on-Chip: Next Generation Electronics

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Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g. on clock skew, by having asynchronous communication between modules. A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms. The authors survey various methodologies used for leveraging asynchronous on-chip communication. They investigate various GALS based implementations, desynchronisation strategies and asynchronous network-on-chip (NoC) designs.

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“…The idea of performing on-chip dynamic routing is described although not yet implemented. MicroNetwork [10] provides on-chip communication via a pipelined interconnect. A rotating resource arbitration scheme is used to coordinate internode transfer for dynamic requests.…”

Section: Related Workmentioning

confidence: 99%

An architecture and compiler for scalable on-chip communication

Liang

Laffely²,

Srinivasan

et al. 2004

IEEE Trans. VLSI Syst.

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Abstract-A dramatic increase in single chip capacity has led to a revolution in on-chip integration. Design reuse and ease of implementation have became important aspects of the design process. This paper describes a new scalable single-chip communication architecture for heterogeneous resources, adaptive system-on-a-chip (aSOC) and supporting software for application mapping. This architecture exhibits hardware simplicity and optimized support for compile-time scheduled communication. To illustrate the benefits of the architecture, four high-bandwidth signal processing applications including an MPEG-2 video encoder and a Doppler radar processor have been mapped to a prototype aSOC device using our design mapping technology. Through experimentation it is shown that aSOC communication outperforms a hierarchical bus-based system-on-chip (SoC) approach by up to a factor of five. A VLSI implementation of the communication architecture indicates clock rates of 400 MHz in 0.18-m technology for sustained on-chip communication. In comparison to previously-published results for an MPEG-2 decoder, our on-chip interconnect shows a runtime improvement of over a factor of four.Index Terms-Communications architecture, on-chip interconnect, system-on-chip (SoC).

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Micronetwork-based integration for SOCs

Cited by 98 publications

References 4 publications

QNoC: QoS architecture and design process for network on chip

QNoC: QoS architecture and design process for network on chip

Asynchronous on-chip networks

An architecture and compiler for scalable on-chip communication

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