Asynchronous on-chip networks

Abstract

Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g. on clock skew, by having asynchronous communication between modules. A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms. The authors survey various methodologies used for leveraging asynchronous on-chip communication. They investigate various GALS based implementations, desynchronisation strategies and asynchronous network-on-chip (NoC) designs.

A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework

“…The acknowledge RTC guarantees that an Ack signal can only be received by the previous pipeline control block after the current pipeline stage has successfully stored the data -e.g. Ack [1] only arrives at Ctrl0 after the input data of Reg1 is successfully stored.…”

“…In modern technology nodes, however, it has become very difficult to design a correct and efficient chip-wide clock distribution tree. In fact, the circuitry required to distribute the clock signal in a high-speed processor accounts, in average, for 45% of total power [1]. Asynchronous circuits are a potential solution for coping with the issues raised by a global control signal, as they do not require a clock, employing local handshaking to perform communication instead.…”

Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits

“…The NoC paradigm has introduced new energy-efficient networks with lower latencies and better performances overall for transferring data in SoCs. An interesting category of NoCs is the asynchronous NoCs (ANoCs) [9], which are mainly implemented in globally asynchronous locally synchronous (GALS) [10,11] architectures-especially for sub-micron technologies. Thanks to the nature of asynchronous logic, these networks can bypass problems caused by the clocking distribution in an SoC, such as clock skew.…”

Asynchronous transient resilient links for NoC

“…Significant effort into the communication between the cores has resulted in extensive research of using Network-on-Chip (NoC) as the communication mechanism [1][2][3]. The NoC consists of switches and network interfaces connected together by links.…”