2015 Euromicro Conference on Digital System Design 2015
DOI: 10.1109/dsd.2015.104
|View full text |Cite
|
Sign up to set email alerts
|

A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework

Abstract: Contemporary silicon technology enables integrating billions of transistors and allows the creation of complex systems-on-chip. At the same time, strict power dissipation budgets and growing interest in high performance battery-powered devices drive the need for energy-efficient high performance circuits. Bundled-data asynchronous circuits are good candidates for high performance low power systems, as they operate with average-case delays and present reduced switching activity when compared to other asynchrono… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
4
0

Year Published

2017
2017
2021
2021

Publication Types

Select...
7
1

Relationship

0
8

Authors

Journals

citations
Cited by 15 publications
(4 citation statements)
references
References 18 publications
0
4
0
Order By: Relevance
“…Indeed, all neuromorphic systems embedding asynchronous logic rely on a custom tool flow (e.g., see [71]- [75]), which increases the design time and requires support from a team experienced in asynchronous logic design. Therefore, solutions to avoid the development of a custom tool flow are increasingly being investigated: in [76]- [78], the application of specific constraints to industrial digital CAD tools allows automatically optimizing the timing closure of asynchronous bundled-data circuits. This idea was recently applied in the context of networkon-chips (NoCs), where Bertozzi et al demonstrate significant power-performance-area improvements for asynchronous NoCs compared to synchronous ones, while maintaining an automated flow based on standard CAD tools [79].…”
Section: B Digital Designmentioning
confidence: 99%
“…Indeed, all neuromorphic systems embedding asynchronous logic rely on a custom tool flow (e.g., see [71]- [75]), which increases the design time and requires support from a team experienced in asynchronous logic design. Therefore, solutions to avoid the development of a custom tool flow are increasingly being investigated: in [76]- [78], the application of specific constraints to industrial digital CAD tools allows automatically optimizing the timing closure of asynchronous bundled-data circuits. This idea was recently applied in the context of networkon-chips (NoCs), where Bertozzi et al demonstrate significant power-performance-area improvements for asynchronous NoCs compared to synchronous ones, while maintaining an automated flow based on standard CAD tools [79].…”
Section: B Digital Designmentioning
confidence: 99%
“…This track operates with commercial CAD tools and under the normal hardware description languages (HDLs) [23]. For example, the work in [24] aimed at improving the process of identifying and setting relative timing constraints (RTCs) using the available tools. Modifications to both the logical synthesis flow and the physical implementation were implemented for Synopsys tools.…”
Section: Related Workmentioning
confidence: 99%
“…Ghiribaldi et al [5] describe an iterative synthesis flow based on common CAD synthesis tools, which expects a description in common hardware description languages. Gibiluka et al [7] proposed a framework [12] and based on [6]) with a similar approach, which utilizes a XML description of the necessary RTCs and enables the automated fulfillment of these constraints during synthesis. However, in most publications, no detailed information, such as circuit description level or the utilized synthesis process, is given about the procedure of the synthesis flow.…”
Section: Related Workmentioning
confidence: 99%
“…Common synthesis tools do not support RTCs. However, they can be enforced by an iterative process similar to the approaches proposed by Ghiribaldi et al [5] and Gibiluka et al [7]. To ensure compatibility with the Synopsys design constraints format (SDC), the proposed flow enables the possibility to define paths between pins and/or ports inside the design and RTCs between different paths and groups of paths.…”
Section: Enforcing Relative Timing Constraints (Rtcs)mentioning
confidence: 99%