Micropipelines

Sutherland, Ivan E.

doi:10.1145/1283920.1283946

Cited by 106 publications

(165 citation statements)

References 8 publications

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“…The asynchronous design style used in AMULET1 is based on Sutherland's Micropipelines [2] which employ a 2-phase bundled data interface for sending data between functional units. 2-phase (or transition) signalling uses both rising and falling edges in turn to signal the same event; rising and falling edges are equivalent and carry the same information ( figure 1).…”

Section: Sutherland's Micropipelinesmentioning

confidence: 99%

Computing without Clocks: Micropipelining the ARM Processor

Furber

1995

Asynchronous Digital Circuit Design

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High-performance VLSI microprocessors are becoming very power hungry; this presents an increasing problem of heat removal in desk-top machines and of battery life in portable machines. Asynchronous operation is proposed as a route to more energy efficient computing. In his 1988 Turing Award Lecture, Ivan Sutherland proposed a modular approach to asynchronous design based on "Micropipelines". The AMULET group at Manchester University has developed an asynchronous implementation of the ARM microprocessor based on micropipelines as part of a broad investigation into low power techniques. The design is described in detail, the rationale for the work is presented and the characteristics of the chip described. The first silicon from the design arrived in April 1994 and an evaluation of it is presented here.

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Section: Sutherland's Micropipelinesmentioning

confidence: 99%

Computing without Clocks: Micropipelining the ARM Processor

Furber

1995

Asynchronous Digital Circuit Design

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“…In this paper, we summarize recent developments in asynchronous circuit design and then present our high-level synthesis system, SHILPA 1 . W e will focus on the high-level optimizations used by SHILPA.…”

Section: Introductionmentioning

confidence: 99%

High-level optimizations in compiling process descriptions to asynchronous circuits

Gopalakrishnan

Akella

1994

Journal of VLSI Signal Processing

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Abstract. Asynchronous Self-Timed designs are beginning to attract attention as promising means of dealing with the complexity of modern VLSI technology. In this paper, we present our views on why asynchronous systems matter. We then present details of our high level synthesis tool SHILPA that can automatically synthesize asynchronous circuits from descriptions in our concurrent programming language, hopCP. W e outline many of the novel features of hopCP and also sketch h o w these constructs are compiled into asynchronous circuits, and then focus on the high level optimizations employed by SHILPA, including concurrent guard evaluation and concurrent process decomposition.

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“…Process decomposition does not involve signal-sharing between incompletely specified machines. Signal-sharing is addressed in macromodule based design systems [1,2] by using additional macromodules such as Toggles [15] and Decision-waits [5] to steer the global input to the correct sub-controller. In [3,14], a method called contraction has been suggested as a decomposition technique for signal transition graph (STG) specifications.…”

Section: Related Workmentioning

confidence: 99%

“…Each transition of the Petri-net (except fork and join) is annotated with an action, which can be a two-phase [15] signal transition on an input or output wire (input transition names are underlined), an assignment statement, a Boolean expression (used for choices), or a CSP-style communication primitive. Forkjoin concurrency is allowed within sequential threads.…”

Section: Overview Of Ackmentioning

confidence: 99%

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A technique for synthesizing distributed burst-mode circuits

Kudva¹,

Gopalakrishnan²,

Jacobson³

33rd Design Automation Conference Proceedings, 1996

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We offer a technique to partition a centralized control-flow graph to obtain distributed control in the context of asynchronous highlevel synthesis. The technique targets Huffman-style asynchronous controllers that are customized to the problem. It solves the key problem of handling signals that are shared between the partitions-a problem due to the incompletely specified nature of asynchronous controllers. We report encouraging experimental results on realistic examples.

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Micropipelines

Cited by 106 publications

References 8 publications

Computing without Clocks: Micropipelining the ARM Processor

Computing without Clocks: Micropipelining the ARM Processor

High-level optimizations in compiling process descriptions to asynchronous circuits

A technique for synthesizing distributed burst-mode circuits

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