Microprocessor and FPGA interfaces for in-system co-debugging in field programmable hybrid systems

Aguirre, M.A.; Tombs, J.; Baena-Lecuyer, V.; Mora, J.L.; Carrasco, J.M.; Torralba, A.; Franquelo, Leopoldo G.

doi:10.1016/j.micpro.2004.06.009

Cited by 17 publications

(11 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Indeed, [19] reports 916 seconds to inject 3000 bitflips in one FF and [17] reports 3.5 seconds needed for a FF fault injection in a Xilinx TM Virtex-II FPGA. Another interesting reconfiguration-based system is Fault Tolerant -University of Seville Hardware DEbugging System (FT-UNSHADES), which implements a read-modify-write approach [20], [21]. The reported time to inject and evaluate a fault is on the order of 100 ms (in this case, no information was found only for a single FF fault injection) and it uses the JTAG debugging port to this end.…”

Section: B Reconfiguration-based Fault Injectionmentioning

confidence: 99%

A Methodology to Emulate Single Event Upsets in Flip-Flops Using FPGAs through Partial Reconfiguration and Instrumentation

Serrano

Clemente

Mecha

2015

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

Abstract-This paper presents a methodology to emulate Single Event Upsets (SEUs) in FPGA flip-flops (FFs). Since the content of a FF is not modifiable through the FPGA configuration memory bits, a dedicated design is required for fault injection in the FFs. The method proposed in this paper is a hybrid approach that combines FPGA partial reconfiguration and extra logic added to the circuit under test, without modifying its operation. This approach has been integrated into a fault-injection platform, named NESSY (Non intrusive ErrorS injection SYstem), developed by our research group. Finally, this paper includes results on a Virtex-5 FPGA demonstrating the validity of the method on the ITC'99 benchmark set and a Feed-Forward Equalization (FFE) filter. In comparison with other approaches in the literature, this methodology reduces the resource consumption introduced to carry out the fault injection in FFs, at the cost of adding very little time overhead (1.6 µs per fault).

show abstract

Section: B Reconfiguration-based Fault Injectionmentioning

confidence: 99%

A Methodology to Emulate Single Event Upsets in Flip-Flops Using FPGAs through Partial Reconfiguration and Instrumentation

Serrano

Clemente

Mecha

2015

IEEE Trans. Nucl. Sci.

View full text Add to dashboard Cite

show abstract

“…Time is represented as an ordered set of stimuli that are injected into the FPGA, SEUs are inserted using a read-modify-write strategy of the configuration memory of the FPGA. This scheme is an application of the previous experience UNSHADES-1 and UNSHADES-2 [6][7]. This paper is organized as follows: first, we introduce to the SEU measurement problem.…”

Section: Introduction V Lsi Designs For Critical Industry Applicatmentioning

confidence: 99%

Radiation Environment Emulation for VLSI Designs: A Low Cost Platform based on Xilinx FPGA's

Nápoles

Guzmán

Aguirre

et al. 2007

2007 IEEE International Symposium on Industrial Electronics

Self Cite

View full text Add to dashboard Cite

As technology shrinks, critical industral applications have to be designed with special care. VLSI circuits become more sensitive to ambient radiation: it affects to the internal structures, combinational or sequential elements. The effects, known as Single Event Effects (SEEs), are modeled as spontaneous logical changes in a running netlist. They can be mitigated at netlist design level by means of inserting massive redundancy logic in the IC memory elements, as well as designing robust deadlock-free state machines. Current techniques for the analysis and verification of the protection logic for VLSI are inefficient and expensive, lacking either speed or analysis. This paper presents the FT-UNSHADES system. This system is a low cost emulator focused on bit-flip insertion and SEE analysis at hardware speed, based on a Xilinx Virtex-IT. Radiation tests are emulated in a highly controlled process, using a non-intrusive method. As a result the system can insert and analyse at least 80K faults per hour in a system with 2 million test vectors.

show abstract

“…[5][6][7] These user-programmable solutions are capable of performing the hardware part of a design for a significantly lower price, and they maintain many of the advantages of the ASIC ͑application-specific integrated circuit͒ solutions. FPGA foundries offer many built-in circuit features, such as memory, multipliers, and high-speed communication links.…”

Section: Introductionmentioning

confidence: 99%

“…These devices were recently introduced into the market under the name of programmable system on a chip ͑PSoCs͒. 5 They have a digital programmable section, a microprocessor core, and a programmable analog tile all embedded into them, often together with other specialized modules for communications. As of the writing of this paper, the most modern and largest in size and performance are the E7V CSoC from Triscend, 19 Excalibur from Altera, 20 Virtex 4 from Xilinx, 21 and EPSLIC from Atmel.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Multiple modular very long instruction word processors based on field programmable gate arrays

Brost

Yang

Paindavoine

et al. 2007

J. Electron. Imaging

View full text Add to dashboard Cite

Modern field programmable gate array (FPGA) chips, with their large memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high-density FPGAs, it is now possible to implement a high-performance very long instruction word (VLIW) processor core in an FPGA. This paper describes research results about enabling the DSP TMS320 C6201 model for real-time image processing applications by exploiting FPGA technology. We present a modular DSP C6201 VHDL model with a variable instruction set. We call this new development a minimum mandatory modules ͑M 3 ͒ approach. Our goals are to keep the flexibility of DSP in order to shorten the development cycle and to use the totality of the powerful FPGA resources in order to increase real-time performance. Some common algorithms of image processing and a face tracking in video sequences application were created and validated on an FPGA VirtexII-2000 multimedia board using the development cycle proposed. Our results demonstrate that an algorithm can easily be, in an optimal manner, specified and then automatically converted to VHDL language and implemented on an FPGA device with systemlevel software. This makes our approach suitable for developing codesign environments. Our approach applies some criteria for codesign tools: flexibility, modularity, performance, and reusability. In this paper, the target VLIW processor is the DSP TMS320C6x. Nonetheless, our design cycle can be generalized to other DSP processors. © 2007 SPIE and IS&T.

show abstract

Microprocessor and FPGA interfaces for in-system co-debugging in field programmable hybrid systems

Cited by 17 publications

References 11 publications

A Methodology to Emulate Single Event Upsets in Flip-Flops Using FPGAs through Partial Reconfiguration and Instrumentation

A Methodology to Emulate Single Event Upsets in Flip-Flops Using FPGAs through Partial Reconfiguration and Instrumentation

Radiation Environment Emulation for VLSI Designs: A Low Cost Platform based on Xilinx FPGA's

Multiple modular very long instruction word processors based on field programmable gate arrays

Contact Info

Product

Resources

About