MIHST: A Hardware Technique for Embedded Microprocessor Functional On-Line Self-Test

Bernardi, P.; Ciganda, L.; Sánchez, Ernesto; Reorda, M. Sonza

doi:10.1109/tc.2013.165

Cited by 18 publications

(6 citation statements)

References 23 publications

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“…A recent SBST architecture which is similar to HASTI architecture in some aspects is MIHST [45]. Similar to HASTI, MIHST combines BIST concepts with SBST routines to facilitate testing of embedded processors.…”

Section: Resultsmentioning

confidence: 99%

HASTI: hardware‐assisted functional testing of embedded processors in idle times

Kamran

2019

IET Computers & Digital Techniques

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In the past decades, software-based self-testing (SBST) which is testing of a processing core using its native instructions has attracted much attention. However, efficient SBST of a processing core which is deeply embedded in a multicore architecture is still an open issue. In this study, inspiring from built-in self-test methods, the authors place several number of hardware test components next to the processing cores in order to overcome existing SBST challenges. These test components facilitate quick testing of embedded cores by providing several mechanisms such as virtual fetch, virtual jump, fake load & store, and segmented test application. In order to enable segmented test application, they propose the concept of test snippet and a test snippet generation approach. The result is the capability of testing embedded cores in short idle times leading to efficient online testing of the cores with zero performance overhead. The authors' results show that their test snippet generation approach not only leads to the production of test snippets which are properly fitted the proposed test architecture but also its final fault coverage is comparable and even a little better than the fault coverage of the best existing methods.

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Section: Resultsmentioning

confidence: 99%

HASTI: hardware‐assisted functional testing of embedded processors in idle times

Kamran

2019

IET Computers & Digital Techniques

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“…Several IEEE 1149.1 test controller solutions have been developed over the years [11:12], but little attention has been given to controller architectures proposed as embedded coprocessors. The proposed test coprocessor supports a wide range of online testing applications for embedded systems based on single or multi-core 32-bit MicroBlaze CPUs, from built-in self-test to online fault detection and diagnosis [13].…”

Section: Discussionmentioning

confidence: 99%

A microprogrammed control path architecture for an embedded IEEE 1149.1 test coprocessor

Gebremeskel

Ferreira

2014

Design of Circuits and Integrated Systems

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This paper proposes a test coprocessor for a 32-bit MicroBlaze CPU core. A microprogrammed architecture is used to implement the coprocessor control path, offering a flexible solution that ensures a straightforward expansion of the test command set. The current version supports a set of SVF-like commands that is able to control one built-in IEEE 1149.1 boundary-scan infrastructure. The proposed test coprocessor is useful in a wide range of online test applications, and namely in the case of mission-critical embedded systems, where online fault detection and diagnosis become particularly important.

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“…Each of GAs uses a set of operators (selection-reproduction, crossover, mutation) and an objective fitness function. The fitness function is used for evaluation of each individual population before application of GA operators for creation of a new population [4,7,9]. The fitness definition depends on selected and used coverage metric in SBST test methods based on GA.…”

Section: Related Work To Sbst Methodsmentioning

confidence: 99%

“…Several methods have been published for the SBST tests generation [1][2][3][4][5] and some of them use genetic algorithms (GAs) [6][7][8][9]. Quality of generated tests is solved over the processor model using a hardware description language (HDL), eg VHDL, Verilog and professional simulators or fault simulators based on specified fault models.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Functional Test Generation Method For Processors Using Genetic Algorithms

Hudec

Gramatova

2015

Journal of Electrical Engineering

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The paper presents a new functional test generation method for processors testing based on genetic algorithms and evolutionary strategies. The tests are generated over an instruction set architecture and a processor description. Such functional tests belong to the software-oriented testing. Quality of the tests is evaluated by code coverage of the processor description using simulation. The presented test generation method uses VHDL models of processors and the professional simulator ModelSim. The rules, parameters and fitness functions were defined for various genetic algorithms used in automatic test generation. Functionality and effectiveness were evaluated using the RISC type processor DP32.K e y w o r d s:

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MIHST: A Hardware Technique for Embedded Microprocessor Functional On-Line Self-Test

Cited by 18 publications

References 23 publications

HASTI: hardware‐assisted functional testing of embedded processors in idle times

HASTI: hardware‐assisted functional testing of embedded processors in idle times

A microprogrammed control path architecture for an embedded IEEE 1149.1 test coprocessor

An Efficient Functional Test Generation Method For Processors Using Genetic Algorithms

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