Miller and noise effects in a synchronizing flip-flop

Dike, C.; Burton, Edward A.

doi:10.1109/4.766819

Cited by 101 publications

(101 citation statements)

References 3 publications

Supporting

Mentioning

100

Contrasting

Order By: Relevance

“…5, showing exponential relation of resolution time to the number of events, as well as the computed values of τ . Two regions were identified, corresponding to short delay (SD) and long delay (LD), for better fit of the exponential parameters, as proposed in [3]. All measurements yielded consistent results for τ in the range 96-103psec as shown in Fig.…”

Section: Resultsmentioning

confidence: 72%

See 1 more Smart Citation

An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm

Beer

Ginosar

Priel³

et al. 2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

There is, however, a finite probability that the circuit will not resolve its metastable state correctly within the allowed time.To enable assessing the risk, and to enable the design of reliable synchronizers and systems, models describing the failure mechanisms for latches and flip flops have been developedMost models express the risk of not resolving metastability in terms of the mean time between failures (MTBF) of the circuit (1).Where C F and D F are the receiver and sender frequencies, respectively, τ is the resolution time constant, and W T is a parameter often related to the setup-and-hold time window at the synchronizer input.Desirable values of MTBF depend on the application and range from several years upwards. The parameter τ is predominant in synchronizer characterization since its effect on MTBF is exponential. Hence lower values of τ correspond to a "good" synchronizer while higher values to a "bad" one.Typical values of τ are the same order of magnitude as the gate delay of the technology (often expressed as FO4, the fanout-of-four delay of a standard gate). Evidently, as technology scales, FC and FD increase and to maintain high MTBF (without increasing N) τ must decrease as well.In the past, τ was believed to improve with technology scaling [4]. However, recent measurements [5] [6] indicate that scaling trends of synchronizers should be re-considered: The need to obtain full characterization will be imperative in technologies beyond 45nm. This paper describes a fully digital on-chip characterization circuit to measure synchronization performance. Our work also compares different synchronization circuits and demonstrates that the standard library flip flop achieves better performance relative to other solutions. To demonstrate the system, a 102x78 2 m µ on-chip digital measurement circuit was fabricated in a low power 1.1V 65nm bulk CMOS process (Fig. 9). II PROPOSED CHARACTERIZATION METHODThe measurement consists of sampling the output of the FF-under-test twice: first (X in Fig 2a) by the clock delayed by a factor DL (by means of a delay line) and second (Y) by the negative edge of the clock. The two samples are compared by a XOR gate. A metastability event that resolves during the time window between the delayed and negative edges of the clock (namely an event that did not resolve within the allotted time S) increments the counter (the number of events expected to resolve after the negative edge of the clock is negligible, since a low frequency clock is used). The measurement continues for time period T and thus MTBF is T divided by the counter value.978-1-4244-9474-3/11/$26.00

show abstract

Section: Resultsmentioning

confidence: 72%

“…To enable assessing the risk, and to enable the design of reliable synchronizers and systems, models describing the failure mechanisms for latches and flip flops have been developed [1] [2] [3] Most models express the risk of not resolving metastability in terms of the mean time between failures (MTBF) of the circuit (1).…”

Section: Introductionmentioning

confidence: 99%

An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm

Beer

Ginosar

Priel³

et al. 2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…The MTBF of such a conflict detector can be determined as follows. Assume τ is one inverter delay, W is two inverter delays, and F D =F C (conflict is possible every cycle when the two clocks are about equal frequency), then [12]: That very safe MTBF (quoted in years) scales quite well over a number of process technologies. In fact, even if the time reserved for metastability resolution is halved to about 40 FO4 inverter delays, the MTBF would still safely exceed 10,000 years, an acceptable goal for most SoCs.…”

Section: Metastability Of the Conflict Detectormentioning

confidence: 99%

A Predictive Synchronizer for Periodic Clock Domains

Frank

Ginosar

2004

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. An adaptive predictive clock synchronizer is presented. The synchronizer takes advantage of the periodic nature of clocks in order to predict potential conflicts in advance, and to conditionally employ an input sampling delay to avoid such conflicts. The result is conflict-free synchronization with minimal latency. The adaptive predictive synchronizer adjusts automatically to a wide range of clock frequencies, regardless of whether the transmitter is faster or slower than the receiver. The synchronizer also avoids sampling duplicate data or missing any input.

show abstract

“…wave pipelining), either to avoid distributing high-frequency clocks or to accommodate large delays (e.g. off-chip drivers) where synchronous pipelining is expensive or impractical [1] [2]. In these circuits the quality is determined by clock skew and jitter [9].…”

Section:  Synchronous Transmissionmentioning

confidence: 99%

Studies and a Method to Minimize and Control the Jitter in Optical Based Communication System

Kumar¹,

Sridevi²,

Reddy³

et al. 2013

IJACSA

View full text Add to dashboard Cite

Abstract-In the years, optical communication systems have been using significantly for attractive solutions to the increasing high data rate in telecommunication systems and various other applications. In the present days mostly, two types of communication schemes are using in data communication, namely asynchronous transmission and synchronous transmission depending on their timing and frame format. But both transmission systems are facing complications seriously with the involvement of jitter in data propagation. The jitter can degrade the performance of a transmission system by introducing bit errors and uncontrolled offsets or displacements in the digital signals. The jitter creates problems furiously at high data rate systems. The jitter need to be minimized in the communication system, otherwise it also degrades the performance of the interconnected systems with main circuit. This will happen due to improper synchronization or management of the clock scheme in the communication system. The improper organization of clock scheme propagates fault data and clock scheme to all other interconnected circuits. In the present work a new clock scheme is discussed to minimize the jitter in data propagation.

show abstract

Miller and noise effects in a synchronizing flip-flop

Cited by 101 publications

References 3 publications

An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm

An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm

A Predictive Synchronizer for Periodic Clock Domains

Studies and a Method to Minimize and Control the Jitter in Optical Based Communication System

Contact Info

Product

Resources

About