Min-max placement for large-scale timing optimization

Kahng, Andrew B.; Mantik, Stefanus; Markov, Igor L.

doi:10.1145/505388.505423

Cited by 47 publications

(10 citation statements)

References 24 publications

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“…A common problem with them is their high computational complexity due to excessive number of paths. Path based timing driven placement includes [2] [3] [4] [5] [6] [7]. In [8], an accurate LP based differential timing analysis is proposed to improve the slack on critical paths that are identified by a static timer.…”

Section: Introductionmentioning

confidence: 99%

“…Since timing is inherently path based, an effective net weighting algorithm should be based on path analysis and consider timing propagation. Furthermore, net-based approaches are often done in an ad-hoc manner and have problems with convergence [17] [7]. For instance, while the delay on critical paths decrease, other paths become critical, and this leads to a convergence problem.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A new LP based incremental timing driven placement for high performance designs

Luo

Newmark

Pan

2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advantage of the path-based delay sensitivity with limited-stage slew propagation, thus it enjoys certain hybrid feature of net and path-based timing driven placement. Our LP formulation considers not only cells on the critical paths, but also cells that are logically adjacent to the critical paths (i.e., the criticality ad jacency network) in a unified manner. We further present a timing aware spreading method to preserve timing in legalization for high performance designs. Our algorithm has been tested on a set of 65nm industry circuits from a multi-GHz microprocessor, and shown to achieve much improved timing on hand-tuned circuits.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A new LP based incremental timing driven placement for high performance designs

Luo

Newmark

Pan

2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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“…Circuit delay during placement can be optimized by using buffer insertion, logic replication, or retiming techniques [1][2][3][4]. On the other hand, many techniques [5][6][7][8][9][10][11][12] do not alter the circuit netlist. These techniques often give high weights to or specify physical length constraints for the edges that lie on the critical timing paths of the circuit.…”

Section: Introductionmentioning

confidence: 99%

Timing-driven placement based on monotone cell ordering constraints

Hwang

Pedram

2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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− In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed that most of the paths that cause timing problems in the circuit meander outside the minimum bounding box of the start and end nodes of the path. To limit this undesirable behavior, we impose a physical constraint on the placement problem, i.e., we assign a preferred signal direction to each critical path in the circuit. Starting from an initial placement solution, by using a move-based optimization strategy, these preferred directions force cells to move in a direction that maximizes the monotonic behavior of the timing-critical paths in the new placement solution. To make the direction assignment tractable, we implicitly group all circuit paths into a set of input-output conduits and assign a unique preferred direction to each such conduit. We integrated this idea into a recursive bipartitioning-based placement framework with a min-cut objective function. Experimental results on a set of standard placement benchmarks show that this approach improves the result of a state-of-the-art industrial placement tool for all the benchmark circuits while increasing the wire length by a tolerable amount.

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“…o Existing global placement engines convert timing information into net weights or net constraints which are then used in the global placement formulation [3] [4]. Few methods [6] interleave timing analysis and global placement. Kahng et al [6] use a min-max timing optimization approach that moves cells in order to minimize the maximum of all weighted edge delays, where an edge is the combination of a net and its driver cell; edge delay is modeled by Elmore model.…”

Section: Introductionmentioning

confidence: 99%

How accurately can we model timing in a placement engine?

Chowdhary¹,

Rajagopal²,

Venkatesan³

et al. 2005

Proceedings. 42nd Design Automation Conference, 2005.

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This paper presents a novel placement algorithm for timing optimization based on a new and powerful concept, which we term differential timing analysis. Recognizing that accurate optimization requires timing information from a signoff static timing analyzer, we propose an incremental placement algorithm that uses timing information from a signoff static timing engine. We propose a set of differential timing analysis equations that accurately capture the effect of placement perturbations on changes in timing from the signoff timer. We have fotmutated an incremental placement optimization problem based on differential timing analysis as a single linear programming (LP) problem which is solved to generate thc new timing-optimized placement.Our experiments show that the worst negative slack (WNS) improves by an average of 30% and the total negative slack (TNS) improves by 33% on average for a set of circuits from a 3.0 GHz microprocessor that were already synthesized and placed by a leading industrial physical synthesis tool. We also show that multiple iterations of our engine give further TNS improvements an average improvement of 5 1 %, which implies that our placer will significantly speed up timing convergence.

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Min-max placement for large-scale timing optimization

Cited by 47 publications

References 24 publications

A new LP based incremental timing driven placement for high performance designs

A new LP based incremental timing driven placement for high performance designs

Timing-driven placement based on monotone cell ordering constraints

How accurately can we model timing in a placement engine?

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