Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: $V_{\rm DDmin}$-Aware Dual Supply Voltage Technique

Fuketa, Hiroshi; Hirairi, Koji; Yasufuku, Tadashi; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu

doi:10.1109/tvlsi.2012.2203834

Cited by 4 publications

(4 citation statements)

References 14 publications

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“…The SRAM buffer power is calculated with CACTI (Chen et al, 2012) configured for 32nm. The power consumed by multipliers and adders is taken from (Han et al, 2016) and flipflops from (Fuketa et al, 2013). The link and router power is calculated with Orion2.0 (Kahng et al, 2009).…”

Section: Overall Processor Architecturementioning

confidence: 99%

Mini-batch Serialization: CNN Training with Inter-layer Data Reuse

Lym¹,

Behroozi²,

Wang³

et al. 2018

Preprint

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Training convolutional neural networks (CNNs) requires intense computations and high memory bandwidth. We find that bandwidth today is over-provisioned because most memory accesses in CNN training can be eliminated by rearranging computation to better utilize on-chip buffers and avoid traffic resulting from large per-layer memory footprints. We introduce the MBS CNN training approach that significantly reduces memory traffic by partially serializing mini-batch processing across groups of layers. This optimizes reuse within on-chip buffers and balances both intra-layer and inter-layer reuse. We also introduce the WaveCore CNN training accelerator that effectively trains CNNs in the MBS approach with high functional-unit utilization. Combined, WaveCore and MBS reduce DRAM traffic by 75%, improve performance by 53%, and save 26% system energy for modern deep CNN training compared to conventional training mechanisms and accelerators.

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Section: Overall Processor Architecturementioning

confidence: 99%

Mini-batch Serialization: CNN Training with Inter-layer Data Reuse

Lym¹,

Behroozi²,

Wang³

et al. 2018

Preprint

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“…Unlike the previous work, our approach aggressively lowers the operating voltage to minimize the energy consumption of the FF while ensuring the specific yield target in a presence of the process variation. Fuketa et al [5] experimentally revealed that the V DDmin of FFs is much higher than that of the other logic elements, such as NAND and NOR gates. To achieve the minimum energy consumption, they propose to use different supply voltages for FFs and the other logic elements.…”

Section: A Related Workmentioning

confidence: 99%

“…Fuketa et al [5] shows that the V DDmin of FFs is higher than that of the other logic circuits. Since employing multiple supply voltages for random logic circuits (i.e., using different supply voltages for FFs and the other logic circuits) is expensive, the operating voltage of FFs should be the same as the voltage for the other random logic circuits.…”

Section: Introductionmentioning

confidence: 97%

Variation-aware Flip-Flop energy optimization for ultra low voltage operation

Kamakari

Nishizawa

Ishihara

et al. 2014

2014 27th IEEE International System-on-Chip Conference (SOCC)

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This paper presents an energy optimization method for a Flip-Flop (FF) circuit in a presence of manufacturing process variation. The optimal FF circuit can be obtained by simultaneously scaling the supply voltage and the transistor size with achieving a specific high yield of the circuit. Lowering the supply voltage is one of the most effective approaches for decreasing the energy consumption of the circuit. However, the increased variation in nano scale semiconductor devices causes a malfunction of FFs especially for the very low voltage operation. Therefore, it is a challenging goal for the nano scale FFs to achieve the high yield and extremely low energy consumption simultaneously. This paper proposes an approximation method for accurately estimating a minimum possible operating voltage (V DDmin ) of FFs with a small number of Monte-Carlo trials. After that, for a given FF, we find a set of optimal supply voltage and the transistor sizes, which minimizes the energy consumption of the FF with achieving the specific high-sigma yield (e.g., 5σ yield). Post layout Monte-Carlo simulation results obtained using a commercial 28 nm process technology model demonstrate that the energy consumption of a FF optimized with our approach can be reduced by 17% at the best case with achieving 5σ yield.

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“…Process and packing deals with technology level, routing and layout deals with circuit level. The logical level [2] is between the technological level and system level. encoding, clock gating and the use of parallel architecture, state-machines deals with logical level.…”

Section: Introductionmentioning

confidence: 99%

Real Time Minimum Energy Tracking Techniquies for Digital Load Circuit

N*¹,

Yellampalli²

2019

IJRTE

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Minimization of energy consumption is an important constraint in portable electronic devices such as smart phones or tablet PCs, laptops . With reliable energy measurement and estimation methods and tools, it is possible to accurate prediction of minimum energy consumption at different levels i.e., from circuit to architecture, architecture to system software and system software to application. Energy efficient design requires reducing energy dissipation in all stages of the design process without compromising the system performance and the quality of services..

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Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: $V_{\rm DDmin}$-Aware Dual Supply Voltage Technique

Cited by 4 publications

References 14 publications

Mini-batch Serialization: CNN Training with Inter-layer Data Reuse

Mini-batch Serialization: CNN Training with Inter-layer Data Reuse

Variation-aware Flip-Flop energy optimization for ultra low voltage operation

Real Time Minimum Energy Tracking Techniquies for Digital Load Circuit

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