Minimizing FPGA Reconfiguration Data at Logic Level

Raghuraman, Krishna; Wang, Haibo; Tragoudas, Spyros

doi:10.1109/isqed.2006.87

Cited by 2 publications

(2 citation statements)

References 19 publications

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“…The reconfiguration cost δ(I j , I k ) can be calculated as n − p i=1 y i, j,k . So, the constraint (10) ensures that m is an upper bound for the reconfiguration cost between any pair of instances corresponding to adjacent execution contexts. So, the minimum maximum reconfiguration cost of I can be obtained by minimizing m, as shown in (6).…”

Section: R) Be a Hrs Obtained From A 3sat Instance With A Collection C Of Clauses On A Finite Set U Of Boolean Variables And Let I Be A 4mentioning

confidence: 99%

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Minimum maximum reconfiguration cost problem

Senhadji-Navarro

García-Vargas

2015

Optim Lett

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Section: R) Be a Hrs Obtained From A 3sat Instance With A Collection C Of Clauses On A Finite Set U Of Boolean Variables And Let I Be A 4mentioning

confidence: 99%

“…One of these challenges is the lack of formal models and methodologies for design automation of dynamically reconfigurable systems [1,2]. One of the most critical problems that the designer faces is to minimize the reconfiguration cost with the goal to achieve an optimal performance [10].…”

Section: Introductionmentioning

confidence: 99%

Minimum maximum reconfiguration cost problem

Senhadji-Navarro

García-Vargas

2015

Optim Lett

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Enabling FPGA routing configuration sharing in dynamic partial reconfiguration

Farisi

Heyse

Bruneel

et al. 2014

Des Autom Embed Syst

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Using dynamic partial reconfiguration (DPR), several circuits can be time-multiplexed on the same FPGA region, saving considerable area compared to an implementation without DPR. However, the long reconfiguration time to switch between circuits remains a significant problem. In this work we show that it is possible to significantly reduce this overhead when the number of circuits is limited. We lower the DPR overhead by reducing the number of configuration bits that needs to be reconfigured. This is achieved by keeping a (predetermined) part of the configuration frames of the DPR region constant/static for all circuits and, consequentially, sharing this part of the configuration between all the circuits. We show that this can be done maintaining the possibility to implement completely unrelated circuits in the DPR region. An extension of the Pathfinder algorithm, called StaticRoute, is presented. It is able to route the nets of the different circuits simultaneously in such a way that the routing of the different circuits is the same in the static part and may only differ in the dynamic part. Our approach is evaluated on the architecture of a commercially available SRAM-based FPGA. We explore how the static part in the configuration memory is best chosen and investigate the associated impact on maximum operating clock frequency as the number of circuits increases. Our experiments show that it is possible to make 50 % of the routing configuration static and therefore reduce the routing reconfiguration time by 50 %, without a significant impact on maximum clock frequency of the circuits. This corresponds to a reduction of total reconfiguration time of 34 %

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Minimizing FPGA Reconfiguration Data at Logic Level

Abstract: Abstract

Cited by 2 publications

References 19 publications

Minimum maximum reconfiguration cost problem

Minimum maximum reconfiguration cost problem

Enabling FPGA routing configuration sharing in dynamic partial reconfiguration

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