Minimizing stand-by leakage power in static CMOS circuits

Naidu, S.R.; Jacobs, E.T.A.F.

doi:10.1109/date.2001.915051

Cited by 18 publications

(13 citation statements)

References 6 publications

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“…[6] treated the problem as a satisfiability problem, and applied an incremental SAT solver to find the minimum leakage. An integer linear programming (ILP) approach was proposed in [7]. It can invariably provide 1-4244-1092-4/07/$25.00 © 2007IEEE.…”

Section: Prior Workmentioning

confidence: 99%

Fast Algorithms for Finding Minimum Leakage Vector

Fan

Xue

Zhang

et al. 2007

2007 IEEE International Conference on Integration Technology

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As technology develops, leakage is becoming the dominant part of the total power dissipation, especially when a circuit frequently enters into idle state. Input Vector Control is an effective method to reduce the leakage power. Based on this technique, we present three algorithms to find the Minimum Leakage Vector rapidly, among which the first one is constructed based on the random algorithm. The second is proposed to improve the Quality of Result (QoR) of the first, while the third gets nearly the same QoR as the second, but runs faster than it. Experimental results on ISCAS85 benchmark show that, for the relatively large circuits, our best algorithm can get over 3x runtime improvement compared with Probability-Based (PB) algorithm, a very good one presented in [4], for a practical number of vectors simulated, while the quality of its result is nearly the same as PB's.Index Terms -/RZ 3RZHU ,QSXW 9HFWRU &RQWURO /HDNDJH 3RZHU 0LQLPXP /HDNDJH 9HFWRU

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Section: Prior Workmentioning

confidence: 99%

Fast Algorithms for Finding Minimum Leakage Vector

Fan

Xue

Zhang

et al. 2007

2007 IEEE International Conference on Integration Technology

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“…Stacks of transistors occur naturally in many CMOS gates, and algorithms also exist for introducing them artificially [3] [4]. Other algorithms assign input vectors for standby mode that use stack effect to reduce leakage current [5] [6].…”

Section: Introductionmentioning

confidence: 98%

Design methodology for fine-grained leakage control in MTCMOS

Calhoun

Honoré

Chandrakasan

2003

Proceedings of the 2003 International Symposium on Low Power Electronics and Design - ISLPED '03

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Multi-threshold CMOS is a popular technique for reducing standby leakage power with low delay overhead. MTCMOS designs typically use large sleep devices to reduce standby leakage at the block level. We provide a formal examination of sneak leakage paths and a design methodology that enables gate-level insertion of sleep devices for sequential and combinational circuits. A fabricated 0.13 m, dual V T testchip employs this methodology to implement a low-power FPGA core with gate-level sleep FETs and over 8X measured standby current reduction. The methodology allows local sleep regions that reduce leakage in active CLBs by up to 2.2X (measured) for some CLB configurations.

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“…Without rewriting, the problem is formulated as in [3] using a direct translation from the original circuit to a 0-1 ILP, which is then run with a timeout of 600 seconds. With rewriting, the problem is converted to an AND/INVERTER graph which is amenable to preprocessing and the iterative solve loop using short time-outs.…”

Section: Resultsmentioning

confidence: 99%

“…However, because of the circuit structure, it is generally not possible to put all gates into their lowest leakage state by just controlling the primary inputs. To minimize the overall leakage current, the authors of [3] formulate an integer program over the circuit. For each gate, a number of terms are added to the objective to reflect each possible input state of the gate.…”

Section: Previous Work In Applicationsmentioning

confidence: 99%

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Circuit-based preprocessing of ILP and its applications in leakage minimization and power estimation

Chai¹,

Kuehlmann

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.

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In this paper we discuss the application of circuit-based logical reasoning to simplify optimization problems expressed as integer linear programs (ILP) over circuit states. We demonstrate that a targeted restructuring of the problem formulation based on the circuit topology can significantly improve the performance and capacity of the overall optimization procedure. We further review two distinct application classes, one requiring a feasible, the other an infeasible bound of an ILP solution that cannot be computed optimally within resource limits and present algorithmic approaches to handle them. We use the problems of computing a minimal leakage state and finding the state transition with maximal peak current to exemplify these two unique classes and present results comparing our methods with alternative techniques.

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Minimizing stand-by leakage power in static CMOS circuits

Cited by 18 publications

References 6 publications

Fast Algorithms for Finding Minimum Leakage Vector

Fast Algorithms for Finding Minimum Leakage Vector

Design methodology for fine-grained leakage control in MTCMOS

Circuit-based preprocessing of ILP and its applications in leakage minimization and power estimation

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