Minimizing testing time in scan-path architecture

Edirisooriya, G.; Edirisooriya, S.

doi:10.1109/mwscas.1992.271055

Cited by 1 publication

(2 citation statements)

References 5 publications

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“…If vectors T S [ l ] , T S [ 2 ] , T S [ 3 ] , and TS[4] are shifted serially into the input register, one after the other, the complete test stream entering the circuit through pin S c a n l n is:…”

Section: Introductionmentioning

confidence: 99%

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A heuristic algorithm for the minimization of test application time in digital circuits with boundary-scan capabilities

Evans¹,

Macii²

Proceedings of 8th Mediterranean Electrotechnical Conference on Industrial Applications in Power Systems, Computer Science and

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Abstrisct C o m m o n test pattern generation programs attempt to generate test sets of minimum size. However, they impliicitly assume that each vector be1ongi:ng to the test set is applis8d in parallel t o the primary input pins of the circuit. h i designs with boundary-scan capabilities, this is no Eonger true; in fact, the test vectors are shifted into the input register serially through the scan-in pin. Therefore, O(n. ITS1 ) clock cycles are required to applli to the circuit the com,plet3. test set, where n indicates the length of each input vector and ITS1 represents the size of the test set. T h e t i m : required to apply the test set to the circuit can be reduci:d if the serial test stream is compacted by exploiting sorni: overlapping of the test vectors. In th.is paper we present a heuristic technique for the minimization of a given test set; experimental results are provided to demonstrate thc efiectiveness of our approach.

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Section: Introductionmentioning

confidence: 99%

“…For this reason, heuristic approaches are usually employed. A particularly efficient method has been proposed by G. and S. Edirisooriya in 1993 [3].…”

Section: Introductionmentioning

confidence: 99%

A heuristic algorithm for the minimization of test application time in digital circuits with boundary-scan capabilities

Evans¹,

Macii²

Proceedings of 8th Mediterranean Electrotechnical Conference on Industrial Applications in Power Systems, Computer Science and

View full text Add to dashboard Cite

show abstract

Minimizing testing time in scan-path architecture

Cited by 1 publication

References 5 publications

A heuristic algorithm for the minimization of test application time in digital circuits with boundary-scan capabilities

A heuristic algorithm for the minimization of test application time in digital circuits with boundary-scan capabilities

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