Scan based diagnostic schemes are used to diagnose faults in faulty circuits. Such techniques assume that the scan path itself is fault-free. However, the logic circuitry associated with the scan chain may occupy nearly 30% of a chip area [3] and hence warrants consideration during fault diagnosis. In this work we propose a simple extension to the scan chain to diagnose faults in scan chains.

A new error model that considers both space and time correlation is proposed. An exact closed form expression for aliasing probability is obtained for an arbitrary test lenght for a large class of signature registers. We identifr the minimum register structure that falls into this class.

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Multipath Multistage Interconnection Networks (MINs) have been proposed to increase reliability in shared memory multiprocessor systems. In this letter we address the problem of evenly distributing trafic among surviving switching elements in the presence of witch f&lures.

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