Time and space correlated errors in signature analysis

Edirisooriya, G.; Edirisooriya, S.; Robinson, John P.

doi:10.1109/vtest.1993.313357

Cited by 9 publications

(4 citation statements)

References 26 publications

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“…Recently, the symmetric channel error model has been extended to account for time correlation. The probability of an erroneous response is increased by a constant factor if the previous response has been erroneous [27]. Alias-ing has also been studied for combinational circuits with stuck-open faults and delay faults [28,29],…”

Section: Definitionmentioning

confidence: 99%

Signature Analysis for Test Responses of Sequential Circuits

Stroele

1998

VLSI Design

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Many test schemes use signature analyzers to compact the responses of a circuit under test. Unfortunately, there can be some faulty circuits with erroneous test responses but exactly the same signature as in the fault-free case. Hence, methods are required to determine how many faults become undetectable due to aliasing. Whereas previous work concentrated on combinational circuits, this paper investigates signature analysis for a wide range of sequential circuits, where the errors in successive responses are correlated. It is shown that for almost all faults of these circuits the probability of aliasing in a signature analyzer with k bits asymptotically approaches 2−k or is 0 if a signature analyzer with an irreducible characteristic polynomial is used and certain test lengths are avoided. The limiting value can be used as a good approximation for practical test lengths. These results are particularly useful for advanced built-in self-test techniques with low hardware overhead.

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Section: Definitionmentioning

confidence: 99%

Signature Analysis for Test Responses of Sequential Circuits

Stroele

1998

VLSI Design

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“…Then we can obtain the state R from the following expression. Rj (R m_ 1,i' R0,i ( fl*Rm 1,i Rm 2,i ( fm * Rm 1,i) (11) Now assume that the state R can also be reached from state R k in one clock period in the absence of faults at the outputs of the CUT. Then we can obtain the state Rj from the following expression.…”

Section: Ri -= (R0i R LImentioning

confidence: 99%

“…Rj (Rm_l,k, R0,k ( fl*Rm_l,k Rm-2,k ( fm-* Rm-1,k) (12) From equations (11) The probability of aliasing, Pal is defined as the probability of the MISR initially in the all zero state leaving the all zero state and returning to it [3].…”

Section: Ri -= (R0i R LImentioning

confidence: 99%

“…Aliasing in single input linear feedback shift registers (LFSRs) and MISRs have been studied by several researchers [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] under various bit error models to compute Pal" In this work we use the q-ary error model which considers correlated errors among Circuit Under Test (CUT) outputs 10,15,16]. The q-ary error model assumes that all (2m-l) error patterns possible at the m-output CUT are equally likely.…”

Section: Introductionmentioning

confidence: 99%

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Closed Form Aliasing Probability For Q‐ary Symmetric Errors

Edirisooriya

1996

VLSI Design

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In Built-In Self-Test (BIST) techniques, test data reduction can be achieved using Linear Feedback Shift Registers (LFSRs). A faulty circuit may escape detection due to loss of information inherent to data compaction schemes. This is referred to as aliasing. The probability of aliasing in Multiple-Input Shift-Registers (MISRs) has been studied under various bit error models. By modeling the signature analyzer as a Markov process we show that the closed form expression derived for aliasing probability previously, for MISRs with primitive polynomials under q-ary symmetric error model holds for all MISRs irrespective of their feedback polynomials and for group cellular automata signature analyzers as well. If the erroneous behaviour of a circuit can be modelled with q-ary symmetric errors, then the test circuit complexity and propagation delay associated with the signature analyzer can be minimized by using a set of m single bit LFSRs without increasing the probability of aliasing.

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