2004
DOI: 10.1007/978-3-540-30205-6_31
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Minimizing the Power Consumption of an Asynchronous Multiplier

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(1 citation statement)
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“…1. An asynchronous pipeline using a code-data coding low-power multiplier [14] and the synchronous implementation has the same architecture. The 32 × 32-bit iterative multiplier has two pipeline stages, the first adds 8 partial products together while the second iterates the result, adds the value from the first stage, then shifts the sum right 8 bits.…”
Section: E Fine-grain Clock Gatingmentioning
confidence: 99%
“…1. An asynchronous pipeline using a code-data coding low-power multiplier [14] and the synchronous implementation has the same architecture. The 32 × 32-bit iterative multiplier has two pipeline stages, the first adds 8 partial products together while the second iterates the result, adds the value from the first stage, then shifts the sum right 8 bits.…”
Section: E Fine-grain Clock Gatingmentioning
confidence: 99%