Minimizing the TID effects due to gamma rays by using diamond layout for MOSFETs

Seixas, L. E.; Gonçalez, Odair Lellis; Vaz, Rafael Galhardo; Telles, Antonio Carlos da Costa; Finco, Saulo; Gimenez, Salvador Pinillos

doi:10.1007/s10854-019-00747-w

Cited by 10 publications

(3 citation statements)

References 26 publications

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“…Integrated Circuits) is a project involving many Brazilian research institutions and universities in the studies of ionizing radiation effects on semiconductors and the integrated circuits design by using the Radiation Hardness by Design (RHBD) approach. Among the results of CITAR, many devices with some new layout styles, e.g., the OCTO Metal Oxide Silicon Field Effect Transistors (MOSFETs) and Diamond MOSFETs were proposed and proved to be more tolerant to ionizing radiation than their conventional counterparts [1], [2].…”

Section: Citar (Acronym In Portuguese For Radiation Tolerantmentioning

confidence: 99%

A New Low Cost Current Measurement Circuit with Temperature Compensation

Telles

Emeri

Finco

et al. 2020

JICS

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The electrical characterization of semiconductors devices, when submitted to ionizing radiation should be done in a large range of currents; however, the instrumentation with this ability is very expensive. This work proposes a low-cost circuit using commercial off-the-shelf components (COTS) that enables the measurement of electrical currents in the order of pA range. The circuit presents an output current that is an amplified version of the current to be measured, using the exponential relationship between currents and voltages in Bipolar Junction Transistors (BJTs) and Metal Oxide Silicon Field Effect Transistors (MOSFETs) when operating in the weak inversion region. Furthermore, a block was introduced in order to compensate the gain’s temperature dependence. The results showed that the operating range for the current that will be measured was more than seven decades using BJTs and five decades by using MOSFETs with a high linearity. The circuit version using MOSFETs was able to measure currents as low as 100 fA. The current gain has also good linearity for over five decades. This circuit has a stable behavior for the range of 20 °C to 40 °C, because of the temperature compensation block.

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Section: Citar (Acronym In Portuguese For Radiation Tolerantmentioning

confidence: 99%

A New Low Cost Current Measurement Circuit with Temperature Compensation

Telles

Emeri

Finco

et al. 2020

JICS

Self Cite

View full text Add to dashboard Cite

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“…The research is accomplished by process layout modification, an approach that does not require any additional circuits, logic (speed reduction and area increase) [9,10], or process masks (higher costs) [11]. Radiation tolerance can be achieved just by adding new layers or modifying existing layers, while maintaining the existing CMOS process procedures [12][13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

Modeling and Simulation-Based Layout Optimization for Tolerance to TID Effect on n-MOSFET

Lee

Kim

et al. 2021

Electronics

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In the present study, the layout structure of an n-MOSFET, which is vulnerable to radiation, was designed in a different way to enhance its tolerance to radiation. Radiation damage assessment was conducted using modeling and simulation (M&S) techniques before actual semiconductor process fabrication and radiation tests to verify its tolerance properties. Based on the M&S techniques, the role of each layer was determined to improve the radiation tolerance of semiconductors, and the layout design of an n-MOSFET with enhanced radiation tolerance was optimized. The optimized radiation-tolerant n-MOSFET design was implemented in the 0.18-um CMOS bulk process, and radiation exposure tests were conducted on the device. A cumulative radiation dose up to 2 Mrad(Si) was applied to verify its radiation-tolerant performance. Developing new devices using M&S techniques for radiation damage assessment allows reliable estimates of their electrical and radiation-tolerant properties to be obtained in advance of the actual manufacturing process, thereby minimizing development costs and time.

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“…Utilizar estilos de leiaute inovadores para MOSFETs, é uma abordagem alternativa e praticamente ainda não usada pelas empresas de CIs CMOS. Esses leiautes são capazes de aumentar o desempenho elétrico e a robustez dos dispositivos quanto às variações do processo de fabricação de CIs CMOS e às variações das condições ambientais (GIMENEZ, 2016;SEIXAS et al, 2019;SEIXAS et al, 2017;PERUZZI et al, 2017). O estilo de leiaute do tipo Diamante (formato de porta hexagonal) para MOSFET é outro exemplo dessa nova abordagem (GIMENEZ, 2016;SEIXAS et al, 2019;SEIXAS et al, 2017;PERUZZI et al, 2017;GIMENEZ et al, 2015;GIMENEZ et al, 2015a;GIMENES;ALATI, 2015;GIMENEZ et al, 2014;GIMENEZ et al, 2014a;GIMENEZ et al, 2014b)…”

Section: Vmmounclassified

Otimização de projetos de circuitos integrados cmos analógicos utilizando-se o imtgspice, otas cascateados e mosfets do tipo diamante

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Minimizing the TID effects due to gamma rays by using diamond layout for MOSFETs

Cited by 10 publications

References 26 publications

A New Low Cost Current Measurement Circuit with Temperature Compensation

A New Low Cost Current Measurement Circuit with Temperature Compensation

Modeling and Simulation-Based Layout Optimization for Tolerance to TID Effect on n-MOSFET

Otimização de projetos de circuitos integrados cmos analógicos utilizando-se o imtgspice, otas cascateados e mosfets do tipo diamante

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