Minimum energy for computation, theory vs. experiment

Nanoengineering: Fabrication, Properties, Optics, and Devices XIV

Samaali

et al. 2017

CMOS technology allows a femto Joule energy dissipation per logic operation, if operated at optimal frequency and voltage. However, this value remains orders of magnitude above the theoretical limit predicted by Landauer. In this work, we present a new paradigm for low power computation, based on variable capacitors. Such components can be implemented with existing MEMS technologies. We show how a smooth capacitance modulation allows an energy-efficient transfer of information through the circuit. By removing electrical contacts, our method limits the current leakages and the associated energy loss. Therefore, capacitive logic must be able to achieve extremely low power dissipation when driven adiabatically. Contactless capacitive logic also promises a better reliability than systems based on MEMS nanorelays.

Section: Introductionmentioning

confidence: 99%

Contactless capacitive adiabatic logic

Nanoengineering: Fabrication, Properties, Optics, and Devices XIV

Samaali

et al. 2017

“…Even though Landauer's theory is still being discussed, it is possible to decrease the energy required to implement the logical operation at the hardware level. Adiabatic logic based on FET has been introduced to alleviate this inherent trade-off and reduce the conduction loss [3]. By smoothing transitions between logic states, the charge and discharge of the FET gate capacitance C through the FET channel resistance R of the previous stage is lowered by a factor of 2RC…”

Section: Introductionmentioning

confidence: 99%

Capacitive-Based Adiabatic Logic

Fanet

et al. 2017

Reversible Computation

This paper introduces a new paradigm to implement logic gates based on variable capacitance components instead of transistor elements. Using variable capacitors and Bennett clocking, this new logic family is able to discriminate logic states and cascade combinational logic operations. In order to demonstrate this, we use the capacitive voltage divider circuit with the variable capacitor modulated by an input bias state to the set output state. We propose the design of a four-terminal capacitive element which is the building block of this new logic family. Finally, we build a Verilog-A model of an electrically-actuated MEMS capacitive element and analyze the energy transfer and losses within this device during adiabatic actuation. The proposed model will be used for capacitive-based adiabatic logic circuit design and analysis, including construction of reversible gates.

“…Even though Landauer's theory is still being discussed [2], it is possible to decrease the energy required to implement the logical operation at the hardware level. Adiabatic logic based on FET transistors has been introduced to alleviate this inherent trade-off and reduce the conduction loss [3], [4]. By smoothing transitions between logic states, the charge and discharge of the FET gate capacitance C through the FET channel resistance R of the previous stage is lowered by a factor of 2RC T , where T is the ramp duration.…”

Section: Introductionmentioning

confidence: 99%

Capacitive adiabatic logic based on gap-closing MEMS devices

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

Samaali

et al. 2017

This paper presents the energy analysis of capacitive adiabatic logic (CAL) based on gap-closing MEMS devices. CAL uses variable capacitance components instead of transistor elements to have a new balance between on-and off-state losses. Ultra-low power consumption in CAL requires an energy efficient way for charging and discharging of the variable capacitance. First, we investigate "pure" electrical model of the two-terminal variable-gap capacitor and demonstrate that any hysteresis in CV-characteristic leads to losses of the stored energy. Next, we propose the design of a four-terminal gap-closing MEMS capacitive element to implement variable capacitance element for CAL and build its Verilog-A compact model. Further, we analyze the energy transfer and losses within this device during adiabatic charging and discharging. The received results demonstrate that the variable gap devices with hysteresis have a non-adiabatic losses during operation with four-phase power clock. Finally, the cascadability of the signal throw buffer chain is presented.