Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study

Abstract

Abstract-This paper addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain. The paper presents a generic implementation template using bundled-data circuitry and current sensing completion detection. To support this, a fully-decoupled latch controller has been developed, which integrates the current sensing circuitry. The paper outlines a corresponding design flow, which is based on contemporary synchronous EDA tools, and which transforms a synchronous design, into a corresponding self-timed circuit. The design flow and the current-sensing technique is validated by the implementation of an asynchronous version of a wavelet based event detector for cardiac pacemaker applications in a standard 65 nm CMOS process. The chip has been fabricated and the area overhead due to power domain separation and completion detection circuitry is 13.6 %. The improvement in throughput due to asynchronous operation is 52.58 %. By trading the throughput improvement, energy dissipation is reduced by 16.8 % at the energy-minimum supply voltage.

High-Level Energy Estimation in the Sub-V<formula formulatype="inline"><tex Notation="TeX">$_{{\rm T}}$</tex></formula> Domain: Simulation and Measurement of a Cardiac Event Detector

“…The measured cores are identical; however, the ASIC in [21] has a sensing transistor in the supply rails. Speed degradation of 40% occurs due to this transistor and is taken into consideration in our analysis.…”

“…7 represents the block referred to as col i in Fig. 4, which needs to be replicated six times to realize the multiplication with the columns of the matrix in (21). To simplify the implementation, the matrix coefficients are replaced with rounded integer values, which do not degrade detection performance.…”

“…The energy is measured on ASIC samples, which were available in an earlier tapeout [21], [22], where the ASIC cores could be triggered by a synchronous clock or in a self-timed manner depending on the implementation. The measured cores are identical; however, the ASIC in [21] has a sensing transistor in the supply rails.…”

Magnetic Random Access Memory based non-volatile asynchronous Muller cell for ultra-low power autonomous applications

“…The asynchronous communication is proved to be a better solution for the ultra-low power applications, since it can significantly reduce the dynamic power consumption. 3 Comparing to much more conventional synchronous communication, it has smaller transition activity, and when there is no computational task, it naturally remains in an idle state, consuming only static power due to the leakage of the transistors. It is very important to note, that the synchronous approach is always limited by the worst-case delays: while the datapath with the critical delay will finish the computation all other datapaths are waiting and consuming static power.…”

On Dual-Rail Control Logic for Enhanced Circuit Robustness

“…Designers usually prefer using complex gates, which can be implemented as the so-called generalised (or asymmetric) C-elements [30]. This way many control circuits published to date, such as controllers for pipeline stages [30], NoC routers [13], as well as controllers for latches for subthreshold logic [1], have been constructed. However, in the sub-threshold mode, even these SI/QDI implementations may become vulnerable to the effects of variability or susceptibility to noise (cross-talk) and transient faults.…”