High-Level Energy Estimation in the Sub-V<formula formulatype="inline"><tex Notation="TeX">$_{{\rm T}}$</tex></formula> Domain: Simulation and Measurement of a Cardiac Event Detector

Abstract

Abstract-This paper presents a flow that is suitable to estimate energy dissipation of digital standard-cell based designs which are determined to operate in the subthreshold regime. The flow is applicable on gate-level netlists, where back-annotated toggle information is used to find the minimum energy operation point, corresponding maximum clock frequency, as well as the dissipated energy per clock cycle. The application of the model is demonstrated by exploring the energy efficiency of pipelining, retiming, and register balancing. Simulation results, which are obtained during a fraction of SPICE simulation time, are validated by measurements on a wavelet-based cardiac event detector that was fabricated in 65-nm low-leakage high-threshold technology. The mean of the absolute modeling error is calculated as 5.2%, with a standard deviation of 6.6% over the measurement points. The cardiac event detector dissipates 0.88 pJ/sample at a supply voltage of 320 mV.

Synthesis strategies for sub-V<inf>T</inf> systems

“…Fig. 2 shows d norm (V DD ) for all timing arcs of all standardcells in a reference design [9]. In contrast to the basic assumption of the sub-V T frequency model in [8,9], we find that d norm (V DD ) can be significantly larger than one and increases notably for most standard-cells when scaling down V DD .…”

“…1(a), the first method starts from a regular static timing analysis (STA) and voltage-change dump (VCD)-based power analysis of a fully placed, routed, and back-annotated netlist in the above-V T domain. An analytical model [8,9] is then used to scale timing and power quantities to the sub-V T domain. A main advantage of this analytical model is the ability to immediatly find the EMV.…”

“…The analytical sub-V T frequency model in [8,9] makes the assumption that the propagation delay(s) d cell of all standardcells slow down at the same pace as the propagation delay d inv of a basic inverter when the supply voltage V DD is gradually scaled down. In other words, the ratio d cell /d inv is assumed to be independent of V DD .…”

Benchmarking of Standard-Cell Based Memories in the Sub-$V_{\rm T}$ Domain in 65-nm CMOS Technology

“…Furthermore, accuracy of the model is validated by measurements in [6] and [20]. It is shown that the measured energy is in the near vicinity of the simulated energy dissipation.…”

TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing

“…2) Instruction Set: The instruction set architecture (ISA) comprises a total of 14 All ALU instructions work on 3 operands, using the exact same addressing mode options for each instruction, which helps to reduce complexity of the architecture, since the operand fetch logic and the arithmetic operation are completely decoupled. The supported addressing modes are register direct, register indirect (with pre-or post-increment and decrement) as well as register indirect with offset.…”