Minimum padding to satisfy short path constraints

Shenoy, Narendra; Brayton, Robert K.; Sangiovanni‐Vincentelli, Alberto

doi:10.1109/iccad.1993.580048

Cited by 70 publications

(95 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Yet the experimental results did not show radical improvement. The other method is greedy heuristics, first referred to in [2,3]. The method in [2] decided locations with the maximum setup margin to maintain the minimum clock period but was area consuming and abandoned in today's nano-scale designs.…”

Section: Introductionmentioning

confidence: 99%

“…This method was first proposed in [2] and was preferred by later works because this mathematical approach had optimal solutions. However, compute cost grew exponentially with circuits scaling larger, and became impractical when dealing with VLSI circuits [6].…”

Section: Introductionmentioning

confidence: 99%

“…Short paths padding algorithms have basically two directions: one is ILP (Integer Linear Programming) formulation, by solving equations constructed from timing constraints [2,4,8]. This method was first proposed in [2] and was preferred by later works because this mathematical approach had optimal solutions.…”

Section: Introductionmentioning

confidence: 99%

“…The other method is greedy heuristics, first referred to in [2,3]. The method in [2] decided locations with the maximum setup margin to maintain the minimum clock period but was area consuming and abandoned in today's nano-scale designs. [3] chose locations with the max number of violated paths to maximize the benefit of buffer insertions.…”

Section: Introductionmentioning

confidence: 99%

“…*, No. *, [1][2][3][4][5][6][7][8][9][10][11][12] E that connects all vectors. As illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs

Meng

Chen

et al. 2018

IEICE Electron. Express

View full text Add to dashboard Cite

Abstract:Among prior short paths padding algorithms, greedy heuristic based on the number of short paths had been proven to be area saving and fast. For ultra-low supply multi-voltage designs, however, delay buffers explode due to improper padding locations caused by unconsidered delay variations. To overcome this problem, we propose a new evaluation function "effectiveness" for greedy heuristic, to characterize the benefit of buffer insertion, thereby to optimize the allocation of padding delay and reduce buffer overhead. An improved algorithm to dynamically update slacks during delay assignment stage is also introduced. Experimental results show average area reduction of 91.6% compared to the prior method.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…*, No. *, [1][2][3][4][5][6][7][8][9][10][11][12] E that connects all vectors. As illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs

Meng

Chen

et al. 2018

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

Timing Optimization Through Clock Skew Scheduling

2009

View full text Add to dashboard Cite

Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.

Neuberger¹,

Wirth²,

Kastensmidt³

et al. 2009

VLSI-SoC: Advanced Topics on Systems on a Chip

View full text Add to dashboard Cite

Abstract. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we investigate the variability of flip-flop race immunity in 130nm and 90nm low power CMOS technologies. An on-chip measurement technique with resolution of ~1ps is used to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Statistical die-to-die variations of hold time violations are measured in various register-to-register configurations and show overall 3σ die-to-die standard deviations of 12-16%. Mathematical methods to separate the measured variability between systematic and random variability are discussed, and the results presented. They show that while systematic variability is the major issue in 130nm, it is significantly decreased in 90nm technology due to better process control. Another important point is that the race immunity decreases about 30% in 90nm, showing that smaller clock skews can lead to violations in 90nm. Normality tests to check if the variability follows a normal Gaussian distribution are also presented.

show abstract

Minimum padding to satisfy short path constraints

Cited by 70 publications

References 6 publications

An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs

An effectiveness-oriented greedy heuristic for padding short paths in ultra-low supply voltage designs

Timing Optimization Through Clock Skew Scheduling

Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.

Contact Info

Product

Resources

About