Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS

Abstract

Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based all-digital phaselocked-loops (ADPLL). In this paper, we characterize and analyze the mismatch of cascaded-delay-unit DTCs. Through an improved built-in-self-test (BIST) time-to-digital converter (TDC) assisted with phase-to-frequency detector (PFD), a measurement system of sub-half-ps accuracy is constructed to conduct the characterization. Fabricated in 28-nm CMOS, the DTC transfer functions are measured, and mismatches are compared against Monte-Carlo simulation results. The integral nonlinearity (INL) results are compared against each other and converted to the in-band fractional spur level when the DTC would be deployed in the ADPLL. The BIST-TDC system thus characterizes the on-chip delays without expensive equipment or complex setup. The effectiveness of adding a PFD into the loop is validated. The entire BIST system consumes 0.6 mW with a system self-calibration algorithm to tackle the analog blocks' nonlinearities.

Research on Cosine-Sum Windows with Maximum Side-Lobe Decay for High Precision ADC Spectral Testing

“…It is challenging to achieve coherent sampling for a high precision ADC. Especially for a built-in self-test (BIST) [7][8][9][10][11], it is difficult to integrate a high-performance signal and clock generator due to the limitation of the chip area. Therefore, there is an urgent demand for a testing method that eliminates the requirement of coherent sampling.…”