1996
DOI: 10.1007/bf00158852
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Mixed analog/digital matrix-vector multiplier for neural network synapses

Abstract: In this work we present a hardware efficient matrix-vector multiplier architecture for artificial neural networks with digitally stored synapse strengths. We present a novel technique for manipulating bipolar inputs based on an analog two's complements method and an accurate current rectifier/sign detector. Measurements on a CMOS test chip are presented and validates the techniques. Further, we propose to use an analog extension, based on a simple capacitive storage, for enhancing weight resolution during lear… Show more

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Cited by 21 publications
(8 citation statements)
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“…These include digital [32–34], analog [35,36], hybrid [37,38], FPGA based [39–41], and (non-electronic) optical implementations [4244]. …”
Section: Future Implementation: Hardware Neural Networkmentioning
confidence: 99%
“…These include digital [32–34], analog [35,36], hybrid [37,38], FPGA based [39–41], and (non-electronic) optical implementations [4244]. …”
Section: Future Implementation: Hardware Neural Networkmentioning
confidence: 99%
“…Categorized by storage types, there are five kinds of synapse circuits: capacitor only [1], [7]- [11], capacitor with refreshment [12]- [14], capacitor with EEPROM [4], digital [15], [16], and mixed D/A [17] circuits.…”
Section: B Synapse Circuitsmentioning
confidence: 99%
“…Here are some issues that have been studied and explored in many researches. These include digital [3,4,14], analog [5,6], hybrid [7,8], FPGA based [9][10][11], and (non-electronic) optical implementations [12,13].…”
Section: Introductionmentioning
confidence: 99%