Mixed-Cell-Height Legalization on CPU-GPU Heterogeneous Systems

Heng, Y.; Fung, Kit; Zhao, Yuxuan; Lin, Yibo; Yu, Bei

doi:10.23919/date54114.2022.9774671

Cited by 3 publications

(1 citation statement)

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“…The final layout will be decomposed into three masks colored with different colors. successful applications use GPU to accelerate the design automation tasks, e.g., mask optimization, [24][25][26][27][28][29] design space exploration, [30][31][32][33] and layout generation. [34][35][36] Recent work pioneers using GPU and deep learning on pre or-post process of MPLD.…”

Section: Introductionmentioning

confidence: 99%

GPU accelerated matrix cover algorithm for multiple patterning layout decomposition

Chen

Yang

2023

DTCO and Computational Patterning II

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Multiple patterning lithography (MPL) is regarded as one of the most promising ways of overcoming the resolution limitations of conventional optical lithography due to the delay of next-generation lithography technology. As the feature size continues to decrease, layout decomposition for multiple patterning lithography (MPLD) technology is becoming increasingly crucial for improving the manufacturability in advanced nodes. The decomposition process refers to assigning the layout features to different mask layers according to the design rules and density requirements. When the number of masks k ≥ 3, the MPLD problems are N P-hard and thus may suffer from runtime overhead for practical designs. However, the number of layout patterns is increasing exponentially in industrial layouts, which hinders the runtime performance of MPLD models. In this research, we substitute the CPU’s dance link data structure with parallel GPU matrix operations to accelerate the solution for exact coverbased MPLD algorithms. Experimental results demonstrate that our system is capable of full-scale, lightningfast layout decomposition, which can achieve more than 10× speed-up without quality degradation compared to state-of-the-art layout decomposition methods.

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