Mixed RL-Huffman encoding for power reduction and data compression in scan test

Tehranipour, M.H.; Nourani, Mehrdad; Arabi, K.; Afzali-Kusha, Ali

doi:10.1109/iscas.2004.1329363

Cited by 19 publications

(13 citation statements)

References 18 publications

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“…The Code-based schemes [4], [5], [6], [7], [8], [9], [10] use data compression codes to encode test cubes. The original data is partitioned into symbols; each replaced with a code word to form compressed data.…”

Section: Literature Surveymentioning

confidence: 99%

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Binary Difference Based Test Data Compression for NoC Based SoCs

Chaki

Giri

Rahaman

2012

2012 IEEE Computer Society Annual Symposium on VLSI

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The scaling of microchip technologies has enabled large scale and very complex systems-on-chip (SoC). The highperformance, flexible, scalable, simple to design and power efficient interconnection network, called the Network-on-chip (NoC), permits the system components to communicate effectively. This communication structure needs to be tested for correctness, which requires handling huge volume of test data. Thus, test data compression has now become essential to reduce test costs. It reduces test data volume which in turn decreases testing time. This work presents a new test data compression method based on binary difference and the corresponding decompression architecture. The major advantages of this compression technique include very high compression ratio, and a low-cost on-chip decoder. The effectiveness of the proposed approach is demonstrated by applying it to the full scan test data set of ISCAS'89 benchmark circuits.

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Section: Literature Surveymentioning

confidence: 99%

“…The best compression obtained using Golomb coding [4] has been included in the table for comparison. Row R-HF [6] shows the results of maximum compression % reported for parameter K (maximum run length block size) using RL-Huffman coding scheme. Row SHC [8] is for Selective Huffman Coding.…”

Section: B Decompression Architecturementioning

confidence: 99%

Binary Difference Based Test Data Compression for NoC Based SoCs

Chaki

Giri

Rahaman

2012

2012 IEEE Computer Society Annual Symposium on VLSI

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“…It utilizes the LOC scheme for test pattern application and Huffman encoding for test pattern compression. While some previous works [5,12,17,16,2,7] take both test power and test compression issues into account, they focus on average rather than launch cycle switching activity reduction.…”

Section: The Proposed Techniquementioning

confidence: 99%

PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment

Lin¹,

Wu²,

Huang³

2008

2008 17th Asian Test Symposium

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This paper presents PHS-Fill, an ATPG technique that reduces (1) power supply noise for scan-based at-speed testing, and (2) test data volume in a Huffman coding based test compression environment. PHS-Fill first identifies the preferred Huffman symbols; these symbols correspond to the test pattern templates that improve test compression and reduces power supply noise at the same time. ATPG then biases its primary input assignments so that the test pattern blocks match the preferred symbols whenever possible. Simulation results on ISCAS89 and ITC99 benchmark circuits show that PHS-Fill is a promising solution.

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“…Code-based scheme involves Golomb code [13], EFDR code [14], RL-Huffman code [15] and dictionary code [16] etc. Broadcast-scanbased scheme contains Illinois scan [17], multiple-input broadcast Scan [18], reconfigurable broadcast scan [19] and virtual scan [20] etc.…”

Section: Introductionmentioning

confidence: 99%

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

Tian

Shen

et al. 2016

IEICE Trans. Inf. & Syst.

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SUMMARYLinear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X bits in deterministic test cubes with 0 or 1 properly before encoding the seed to reduce toggle rate. However, Xfilling will increase the number of specified bits, thus increase the difficulty of seed encoding, what's more, the size of LFSR will increase as well. This paper presents a test frame which takes into consideration both compression ratio and power consumption simultaneously. In the first stage, the proposed reseeding-oriented X-filling proceeds for shift power (shift filling) and capture power (capture filling) reduction. Then, encode the filled test cubes using the proposed Compatible Block Code (CBC). The CBC can X-ize specified bits, namely turning specified bits into X bits, and can resolve the conflict between low-power filling and seed encoding. Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%.

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Mixed RL-Huffman encoding for power reduction and data compression in scan test

Cited by 19 publications

References 18 publications

Binary Difference Based Test Data Compression for NoC Based SoCs

Binary Difference Based Test Data Compression for NoC Based SoCs

PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

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