Mobility Enhancement in Solution‐Processed Transparent Conductive Oxide TFTs due to Electron Donation from Traps in High‐<i>k</i> Gate Dielectrics

Zeumault, Andre; Subramanian, Vivek

doi:10.1002/adfm.201503940

Cited by 90 publications

(78 citation statements)

References 34 publications

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“…Furthermore, here we are not claiming that the benefits to electron mobility stem from the formation of a two‐dimensional electron gas at the interface as has been previously argued, even in thick (340 nm) InGaZnO films . Instead, similar to previous observations made in the ZnO/ZrO 2 system , we explain the mobility enhancement in a semiconductor/insulator heterostructure based on directional electron transfer from the Ga 2 O 3 to the ZnO, supported by work function differences obtained for the isolated films as a function of processing temperature. This also provides additional experimental evidence supporting the existing observations in the literature with regard to TCO/high‐k interactions.…”

Section: Introductionsupporting

confidence: 81%

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Use of high-k encapsulation to improve mobility in trap-limited metal-oxide semiconductors

Zeumault

Subramanian

2017

Phys. Status Solidi B

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Low‐temperature spray‐deposited ZnO films are encapsulated by insulating Ga2O3 films and the resulting electronic properties of heterostructure films and transistors are analyzed and compared to un‐encapsulated ZnO as a function of processing temperature. An enhancement in Hall mobility and field‐effect mobility is observed similar to when high‐k dielectrics are used as gate‐dielectrics in transparent conductive oxide thin‐film transistors except without the presence of undesirable device behavior such as gate‐leakage and hysteresis. Based on a recently proposed theory consisting of electron donation from high‐k dielectrics, work function measurements show that conditions for electron transfer from Ga2O3 to ZnO can be met by optimally‐tuning the deposition temperature of the respective films resulting in an effective doping which is qualitatively similar to modulation doping. As a result, TFTs composed of ZnO/Ga2O3 heterostructures exhibit greatly improved switching characteristics and electron transport relative to the otherwise poor performance of low‐temperature processed ZnO achieved through a simple modification to TFT device structure.

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Section: Introductionsupporting

confidence: 81%

“…Although this effect is very reliably reproduced experimentally , its precise cause is only beginning to be understood. This lack of understanding has led to recent attempts to identify a physical origin .…”

Section: Introductionmentioning

confidence: 99%

Use of high-k encapsulation to improve mobility in trap-limited metal-oxide semiconductors

Zeumault

Subramanian

2017

Phys. Status Solidi B

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“…The trap density at/near the gate-dielectric/ ZnO interface can be estimated by equation (3) to be 1.6×10 12 , 1.2×10 12 and 3.6×10 12 cm −2 for the annealing temperature of 200°C, 300°C and 400°C, respectively, indicating that the relatively good electrical performance of the ZnO-TFT with the annealing temperature of 300°C is mainly attributed to the low trap density at/near the gate-dielectric/ZnO interface. In addition, the devices for the three annealing temperatures exhibit a low voltage operation (<8 V), which is close to the results reported using Al 2 O 3 and Ta 2 O 5 gate dielectrics [11,27], but is higher than that of HfLaO and ZrO 2 gate dielectrics [19,20], implying that the electrical performances of the device need to be further optimized for the requirement of low power application in flexible and wearable electronics. Figure 4 exhibits the hysteresis behavior of transfer characteristics under forward and reverse V GS sweeps, and the threshold-voltage shifts (ΔV th =V th·reverse −V th·forward ) of the samples with different NbLaO annealing temperatures are listed in table 1.…”

Section: Resultssupporting

confidence: 82%

“…Su et al [19] fabricated ZnO TFTs with HfLaO gate dielectric, which resulted in a low operating voltage <3 V and a carrier mobility of 3.5 cm 2 V −1 s −1 . Subramanian et al [20] explored solution-processed ZrO 2 gate dielectric and demonstrated a mobility of 20 cm 2 V −1 s −1 and a low operating voltage <3 V in ZnO TFTs. However, there are several potential disadvantages associated with using high-k gate dielectric in TFTs.…”

Section: Introductionmentioning

confidence: 99%

Effects of annealing temperature of NbLaO gate dielectric on electrical properties of ZnO thin-film transistor

et al. 2017

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A bottom-gate zinc-oxide thin-film transistor (ZnO TFT) with high-k NbLaO as gate dielectric was fabricated on indium tin oxide-coated glass substrate by radio frequency sputtering. The NbLaO gate dielectric was annealed in N 2 at different temperatures (200°C, 300°C, and 400°C) for 30 min to investigate the effects of the annealing temperature on the electrical properties of the device. It is demonstrated that the ZnO TFT annealed at 300°C exhibits the relatively good electrical performance with mobility of 20.5 cm 2 V −1 s −1 , off-state current of 3.4 pA, subthreshold slope of 0.18 V/decade, on/off current ratio of 6.25×10 7 and small hysteresis, which are due to reduction of deep traps in the high-k film or at gate-dielectric/semiconductor interface as supported by using a low-frequency noise analysis.

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“…Unfortunately, the heat issue, [8,11] power dissipation, [7,77] lithographic accuracy, [9] and quantum limit [10] problems will substantially increase the economic costs of further circuit integration, in line with Moore's law. [78][79][80] Significantly, the ferroelectric layer inserted in the gate stack is not only a kind of high-κ electric, but also can prevent the gate leakage effectively by NC effect. High thermal dissipation not only increases energy loss but also weakens the working performance of devices.…”

Section: Moore's Law Facing Severe Challengesmentioning

confidence: 99%

Ferroelectric Negative Capacitance Field Effect Transistor

Wang

et al. 2018

Adv Elect Materials

124

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such as steep subthreshold swing (SS), high switching ratio (I on /I off ), adjustable hysteresis, compatibility with standard semiconductor fabrication processes, and environmental friendliness, promotes NCFET to be a promising candidate to lower power consumption and solve the heat problem in ULSI.As early as the 1960s, the concept of negative capacitance (NC) was proposed in amorphous semiconductor chalcogenides thin film, [25,26] then the NC effect was observed in several devices, such as p-n junctions, [27,28] Schottky diodes, [29,30] metal-insulator-metal diodes, [31] and others. [32][33][34][35] Concretely, the NC effect occurs when the reciprocal of the second derivation of potential energy U with respect to the ferroelectric polarization charge Q F is negative, which is usually achieved during the switching process of ferroelectric polarization. [36,37] NCFET achieves steep SS through the NC voltage amplification effect by adding a ferroelectric layer into the transistor gate stack. [22] NCFET simulation methods vary according to the types of transistor gate structures-metal ferroelectric semiconductor field-effect transistor (MFSFET), metal ferroelectric insulator semiconductor field-effect transistor (MFISFET), and metal ferroelectric metal insulator semiconductor field-effect transistor (MFMISFET). However, the basic principle is to realize a match between the channel charge Q and the ferroelectric polarization charge P, [38][39][40][41][42] no matter what the specific gate structure is.Furthermore, the influencing factors of NCFET's electrical properties have been qualitatively analyzed and summarized according to numerous simulation results. Commonly, a tradeoff exists between SS and hysteresis, [22] and we can design and manipulate the gate structure, [41] ferroelectric thickness (t Fe ), [22] ferroelectric material parameters, [38] silicon doping concentration, [39,43] temperature, [44] work frequency, [45][46][47][48] and high-κ dielectric [23,49,50] to optimize the electrical performance of NCFET and meet specific practical application requirement.The experimental researches on NCFETs can be mainly classified into three categories based on various kinds of ferroelectrics. First, the NCFET based on organic ferroelectric-poly(vinylidene difluoride-trifluoroethylene)[P(VDF-TrFE)], has been experimentally demonstrated, and achieves minimum SS (SS min ) = 13 mV dec −1 with small hysteresis. [51,52] Second, the NCFET based on lead zirconate titanate (PZT), a type of inorganic perovskite-type ferroelectric, exhibits hysteretic switching with With the progress in silicon circuit miniaturization, lowering power consumption becomes the major objective. Supply voltage scaling in ultralargescale integration (ULSI) is limited by the physical barrier termed "Boltzmann Tyranny." Moreover, considerable heat is inevitably generated from the ultrahighly integrated circuit. To solve these problems, a ferroelectric negative capacitance field-effect transistor (Fe-NCFET) is proposed in order to reduce the subthresho...

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Mobility Enhancement in Solution‐Processed Transparent Conductive Oxide TFTs due to Electron Donation from Traps in High‐k Gate Dielectrics

Cited by 90 publications

References 34 publications

Use of high-k encapsulation to improve mobility in trap-limited metal-oxide semiconductors

Use of high-k encapsulation to improve mobility in trap-limited metal-oxide semiconductors

Effects of annealing temperature of NbLaO gate dielectric on electrical properties of ZnO thin-film transistor

Ferroelectric Negative Capacitance Field Effect Transistor

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