Mode-controlled data-flow modeling of real-time memory controllers

Abstract

SDRAM is a shared resource in modern multi-core platforms executing multiple real-time (RT) streaming applications. It is crucial to analyze the minimum guaranteed SDRAM bandwidth to ensure that the requirements of the RT streaming applications are always satisfied. However, deriving the worst-case bandwidth (WCBW) is challenging because of the diverse memory traffic with variable transaction sizes. In fact, existing RT memory controllers either do not efficiently support variable transaction sizes or do not provide an analysis to tightly bound WCBW in their presence. We propose a new mode-controlled data-flow (MCDF) model to capture the command scheduling dependencies of memory transactions with variable sizes. The WCBW can be obtained by employing an existing tool to automatically analyze our MCDF model rather than using existing static analysis techniques, which in contrast to our model are hard to extend to cover different RT memory controllers. Moreover, the MCDF analysis can exploit static information about known transaction sequences provided by the applications or by the memory arbiter. Experimental results show that 77% improvement of WCBW can be achieved compared to the case without known transaction sequences. In addition, the results demonstrate that the proposed MCDF model outperforms state-of-the-art analysis approaches and improves the WCBW by 22% without known transaction sequences. Abstract-SDRAM is a shared resource in modern multi-core platforms executing multiple real-time (RT) streaming applications. It is crucial to analyze the minimum guaranteed SDRAM bandwidth to ensure that the requirements of the RT streaming applications are always satisfied. However, deriving the worst-case bandwidth (WCBW) is challenging because of the diverse memory traffic with variable transaction sizes. In fact, existing RT memory controllers either do not efficiently support variable transaction sizes or do not provide an analysis to tightly bound WCBW in their presence. We propose a new mode-controlled data-flow (MCDF) model to capture the command scheduling dependencies of memory transactions with variable sizes. The WCBW can be obtained by employing an existing tool to automatically analyze our MCDF model rather than using existing static analysis techniques, which in contrast to our model are hard to extend to cover different RT memory controllers. Moreover, the MCDF analysis can exploit static information about known transaction sequences provided by the applications or by the memory arbiter. Experimental results show that 77% improvement of WCBW can be achieved compared to the case without known transaction sequences. In addition, the results demonstrate that the proposed MCDF model outperforms state-of-the-art analysis approaches and improves the WCBW by 22% without known transaction sequences.

Modeling and Verification of Dynamic Command Scheduling for Real-Time Memory Controllers

“…First, the results obtained with Uppaal are validated with the open-source RTMemController tool [20], which has been proven to be equivalent to a cycle-accurate SystemC simulator [22] for capturing the timing behavior of the memory controller. Next, the results are compared to the analysis results of the same memory controller design using (a) the analytical and scheduled approaches presented in [23], and (b) the mode-controlled dataflow (MCDF) model introduced in [24].These techniques were discussed in Section V.…”

“…Executing these traces with the cycle-accurate simulator provides identical WCRT and WCBW results as Uppaal, which speaks for the accuracy of our model. 4) Finally, the proposed TA analysis reduce the WCRT bound by up to 20% and improve the WCBW bound by up to 25% compared to the state-of-the-art [23], [24]. The average improvements of the bounds on WCRT and WCBW are 7.7% and 13.6%, respectively.…”

“…In addition, it assumes that every ACT command collides on the command bus. The dataflow model of [24] provides the WCBW of dynamic command scheduling. It also assumes that the ACT commands always have command-bus collisions, but does not require the ALAP assumption.…”

“…These analysis approaches may not be easy to manually adapt to memory controllers with different mechanisms or memories. Similarly to [24], we shift the manual effort to derive performance bounds from analysis to modeling. In other words, rather than providing a specialized WCRT/WCBW analysis of a memory controller, a specialized model of a memory controller is defined, which is analyzed automatically using state-of-the-art tools.…”

“…In other words, rather than providing a specialized WCRT/WCBW analysis of a memory controller, a specialized model of a memory controller is defined, which is analyzed automatically using state-of-the-art tools. [24] uses dataflow, while this paper uses TA, which is more expressive and results in better bounds.…”