Model based OPC for implant layer patterning considering wafer topography proximity (W3D) effects

Park, Songyi; Youn, Hyungjoo; Chung, No-Young; Maeng, Jaeyeol; Lee, Suk-Joo; Ku, Ja-Hum; Xie, Xiaobo; Lan, Song; Mu, Feng; Vellanki, Venu; Kim, Joobyoung; S, Baron; Liu, Huayu; Hunsche, S.; Woo, Soung-Su; Park, Seung-Hoon; Yoon, Jong-Tai

doi:10.1117/12.918000

Cited by 8 publications

(2 citation statements)

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“…The studies of CD variation of pre-gate implant layers have been experimentally demonstrated [5,6,8] and simulated [7,9,10].The control and optimization of PR profile of post-gate LDD layers, especially in the SRAM area, are demonstrated. Several factors of the implant lithography process that could impact the photoresist profile and the optimization of full-map CD uniformity are studied.…”

Section: Introductionmentioning

confidence: 99%

Studies of Photo Resist Profile Improvement in 28 nm Implanting Layer’s Lithography Process without BARC

Liu

et al. 2014

ECS Trans.

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For 28 nm node and below, implant layer patterning is becoming challenging with node shrinkage, due to decreasing critical dimension and usage of non-uniform reflective substrates without bottom anti-reflection coating (BARC). The ADI CD uniformity of a test feature is dramatically improved by adding BARC to reduce substrate reflection, nevertheless a prevalent LDD loop will not introduce BARC for the concern of cost and process complication reduction. The considerable bottom substrate reflectivity not only causes standing wave in photo resist but also introduces slight footing between the photo resist line and the substrate poly head if the substrate topography is rough (especially in the SRAM region). It is necessary to optimize the photo resist profile even under a very high bottom reflectivity. In this paper, several factors of the implant litho process that could impact the photo resist profile and line width roughness (LWR) are studied, and a comprehensive optimization based on these factors' splits test are defined and adopted in the 28 nm LDD loop litho process. Firstly we changed the mask CD to wafer CD bias and simultaneously modified the exposure dosage to meet the ADI target, which is based on our previous study that larger mask bias and over-dosage exposure will result in better photo resist profile. Secondly we studied the PR profile dependence on temperature of post exposure baking (PEB), we tried out the best temperature setting to improve photoresist footing. Thirdly we slightly shifted the focus offset during exposure away from the best focus defined by process FEM results, so that the photoresist profile is improved and meanwhile maintaining a large enough depth of focus for the process.

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Section: Introductionmentioning

confidence: 99%

Studies of Photo Resist Profile Improvement in 28 nm Implanting Layer’s Lithography Process without BARC

Liu

et al. 2014

ECS Trans.

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“…Various mitigation techniques have been developed in order to continue with the immersion lithography system. Multiple Patterning (MP) [2][3][4] and Optical Proximity Correction (OPC) [5][6][7] are popular techniques to mitigate the distortions due to sub-wavelength feature printing. However, all of these mitigation techniques are reaching their limitations with aggressive scaling down of the feature size leading to the development of Next-Generation Lithography (NGLs) techniques.…”

Section: Introductionmentioning

confidence: 99%

A study on flare minimisation in EUV lithography by post‐layout re‐allocation of wire segments

Paul

Banerjee

Sur-Kolay

2021

IET Circuits, Devices & Syst

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The feature size in Integrated Circuits (ICs) has been scaling down aggressively, thereby posing more challenges in their manufacturability. Conventional immersion lithography using a laser of 193 nm wavelength produces layouts having distortions that degrade performance significantly. To overcome this bottleneck, Next-Generation Lithography (NGL) technologies are being developed. Extreme Ultraviolet Lithography (EUVL), one of the popular NGLs, which uses a light of 13.5 nm wavelength. However, irregularities on the photo reflective surface of clear-field masks used in EUVL, scatter the incident light and cause flare that in turn results in layout pattern distortions and critical dimension (CD) violations. One of the approaches to counter the effect of flare is to utilise dummy metal fills. But this incurs additional mask cost. Herein, a method to reduce the flare variation as well as the average flare distribution for a layout by perturbation of wire segments, without affecting performance at the post-layout phase, is proposed. The results show reductions of 20% and 11% on an average in the flare variation and flare mean, respectively, compared to that for the original layout for two different flare models studied on three standard sets of benchmark suites. Consequently, a reduction in the dummy fill demand of a similar magnitude is thus obtained.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction

et al. 2023

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Model based OPC for implant layer patterning considering wafer topography proximity (W3D) effects

Cited by 8 publications

References 0 publications

Studies of Photo Resist Profile Improvement in 28 nm Implanting Layer’s Lithography Process without BARC

Studies of Photo Resist Profile Improvement in 28 nm Implanting Layer’s Lithography Process without BARC

A study on flare minimisation in EUV lithography by post‐layout re‐allocation of wire segments

Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction

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