Model checking algorithms for analog verification

Abstract

In this contribution we present the first method for model checking on nonlinear analog systems. Based on digital CTL model checking algorithms and results in hybrid model checking, we have developed a concept to adapt these ideas to analog systems. Using an automatic state space subdivision method the continuous state space is transfered into a discrete model. In doing this, the most challenging task is to retain the essential nonlinear behavior of the analog system. To describe analog specification properties, an extension to the CTL language is needed. Two small examples show the properties and advantages of this new method and the capability of the implemented prototype tool.

Three-valued automated reasoning on analog properties

“…A natural way to apply model checking to the context of analog circuits verification is the extraction of some finite digital abstraction from the corresponding analog model. Such an approach has been adopted in [5], where the authors qualitatively proved its effectiveness by applying it to some concrete (and well-understood) examples. As part of their work, the authors proposed an enrichment of classical temporal logic languages, recognizing the inadequacy of the latter to model analog properties.…”

“…As part of their work, the authors proposed an enrichment of classical temporal logic languages, recognizing the inadequacy of the latter to model analog properties. However, their extension is still not satisfactory: As an example, simple properties comparing the values of analog variables along their evolution can still not be dealt with in [5]. Indeed, even if a constraint of the kind x < y could be expressed in [5], a major problem to its verification would be the impossibility to define grid abstractions of the analog system's (infinite) state-space, such that on each grid box, the property is either true or false.…”

“…The latter problem-fundamental in the spirit of formal verification techniques-is indeed not taken in consideration in [5]. It can be proved that their framework allows to preserve only truth of universal quantified properties from the abstract to the concrete models.…”

“…However, a symmetrical extreme parameter model in which input variables are admitted to assume any value while the system evolves, could be also easily considered for the abstraction generation. Note that the same extreme input models were adopted in [5]. the base of the three-valued classic CTL model checking for digital systems [1].…”

AMS SoC Formal Verification based on Hybrid Scheme

“…the analog parts and digital parts. In [8], a novel method of symbol computing is proposed for property verification of AMS design. The major idea is to verify AMS design using the same way as SAT, BDD based formal verification for digital system, to verify system automatically.…”