Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits

Mukhopadhyay, Saibal; Bhunia, Swarup; Roy, Kaushik

doi:10.1109/date.2005.210

Cited by 19 publications

(11 citation statements)

References 15 publications

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“…In Mukhopadhyay et al (2003), the authors have studied the effect of gate tunnelling current in ultra-thin gate oxide MOS devices. An analysis of the loading effect on leakage and a method of estimation of the total leakage in a logic circuit is proposed in Mukhopadhyay et al (2005). In Maitra and Bhat (2003), the authors propose analytical schemes to combine the channel and edge components of the gate oxide direct tunnelling current.…”

Section: Contributions Of This Paper and Related Researchmentioning

confidence: 99%

A comparative study on gate leakage and performance of high-𝛋 nano-CMOS logic gates

Kougianos¹,

Mohanty

2010

International Journal of Electronics

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This paper provides a novel attempt to evaluate the gate leakage and delay characteristics of CMOS transistors and logic gates with various alternative highk gate dielectrics, which are replacing SiO 2 in traditional nanoscale MOSFETs. Results have been obtained for both fixed as well as variable loads. The assumption that all gates drive the same load is considered in order to provide a fair comparison of the effect of the variation of design and process parameters, especially that of different high-k dielectrics on the gate direct tunnelling current and propagation delay. On the other hand, the variable loading effect considers a set of practical loading conditions for the logic gates. An exhaustive comparison of all cases finally presents concluding evidence that the tunnelling current is independent of the loading conditions. On the other hand, there is an increase in the delay as the dielectric constant of the gate material, and consequently the load on the device, increases. Ultimately, this paper presents fast and accurate models for on-the-fly calculation of tunnelling current and delay with the aim of integrating them into design automation tools.

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Section: Contributions Of This Paper and Related Researchmentioning

confidence: 99%

A comparative study on gate leakage and performance of high-𝛋 nano-CMOS logic gates

Kougianos¹,

Mohanty

2010

International Journal of Electronics

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“…The impact of loading effect has been presented in [3,4]. We assume that the gate leakage current which is determined by the operational state of the transistors constituting the CMOS gate does not vary with parameters other than input signal values [5].…”

Section: A Overall Leakage Computationmentioning

confidence: 99%

Don’t care filling for power minimization in VLSI circuit testing

Maiti¹,

Chattopadhyay

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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Power minimization is one of the very important issues in the testing of power constrained VLSI circuit. While existing literature emphasizes dynamic power reduction, leakage power is assuming more and more importance in the forthcoming technologies beyond 100 nm. This paper studies the effect of don't care filling of the patterns generated via automated test pattern generators, to make the patterns consume lesser power. It presents a trade-off in the dynamic and static power consumption. Judicious selection of don't cares can provide a trade-off of 17% dynamic power. For static power the trade-off is about 2.4% in the 0.18 μm technology. The effect is expected to be more prominent for technologies beyond 100 nm.

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“…Sub-threshold leakage, gate leakage and reverse biased drain substrate junction band-to-bandtunnelling leakage are the major mechanisms that contribute to the total leakage current [5,6]. Hence, each component depends differently on the transistor geometry such as gate length, source-drain extension length, oxide thickness, junction depth, width, doping profile (channel doping and "halo" doping concentration, flat band voltage and supply voltage) [5,6]. Statistical variation in each of these parameters results in large variation in each of the leakage components, thereby, causing significant increase in the nominal leakage.…”

Section: Introductionmentioning

confidence: 99%

Optimal solution in producing 32-nm CMOS technology transistor with desired leakage current

Elgomati¹

2011

Semicond. Phys. Quantum Electron. Optoelectron.

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Abstract. The objective of this paper is to optimize the process parameters of 32-nm CMOS process to get minimum leakage current. Four process parameters were chosen, namely: (i) source-drain implantation, (ii) source-drain compensation implantation, (iii) halo implantation time, and (iv) silicide annealing time. The Taguchi method technique was used to design the experiment. Two noise factors were used that consist of four measurements for each row of experiment in the L 9 array, thus leading to a set of experiments consisting of 36 runs. The simulator of ATHENA and ATLAS were used for MOSFET fabrication process and electrical characterization, respectively. The results clearly show that the compensation implantation (46%) has the most dominant impact on the resulting leakage current in NMOS device, whereas source-drain (S/D) implantation was the second ranking factor (35%). The percent effects on signal-to-noise ratio (SNR) of silicide annealing temperature and halo implantation are much lower being 12% and 7%, respectively. For the PMOS device, halo implantation was defined as an adjustment factor because of its minimal effect on SNR and highest on the means (43%). Halo implantation doping as the optimum solution for fabricating the 32-nm NMOS transistor is 2.38×10 13 atom/cm 3 . As conclusion, this experiment proves that the Taguchi analysis can be effectively used in finding the optimum solution in producing 32-nm CMOS transistor with acceptable leakage current, well within International Technology Roadmap for Semiconductor (ITRS) prediction.

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Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits

Abstract: In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT)

Cited by 19 publications

References 15 publications

A comparative study on gate leakage and performance of high-𝛋 nano-CMOS logic gates

A comparative study on gate leakage and performance of high-𝛋 nano-CMOS logic gates

Don’t care filling for power minimization in VLSI circuit testing

Optimal solution in producing 32-nm CMOS technology transistor with desired leakage current

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