Modeling and Analysis of Passive Switching Crossbar Arrays

Fouda, Mohammed E.; Eltawil, Ahmed M.; Kurdahi, Fadi

doi:10.1109/tcsi.2017.2714101

Cited by 63 publications

(52 citation statements)

References 43 publications

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“…These voltage drops are functions of the stored data and the wire resistance. At the expected feature size of F = 5nm of RRAMs, the wire resistance per cell reaches as high as 90Ω [4]. Fig.…”

Section: Introductionmentioning

confidence: 93%

“…The encoded output symbol z in+j , 0 ≤ i < m, 0 ≤ j < n, is stored at the (i, j)-th entry in the crossbar array (i.e., we vectorize the array row by row). Instead of using high-level models for the sneak path problem, such as in [6], [7], we use a SPICE-like simulator that is built based on accurate modeling of the resistive crossbar array [4]. This numerical simulator offers a fast alternative to SPICE simulators while maintaining the same simulation accuracy.…”

Section: Application To Resistive Crossbar Arrays a General Framentioning

confidence: 99%

“…Fig. 2a shows the measured current of each cell in a (32 × 32) array with 25Ω wire resistance, storing random data, which is generated by the SPICE-like simulator of [4]. Due to sneak path, the sensed current of low resistance state decreases in both vertical and horizontal directions in the array.…”

Section: Introductionmentioning

confidence: 99%

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Non-Stationary Polar Codes for Resistive Memories

Zorgui

Fouda²,

Wang³

et al. 2019

2019 IEEE Global Communications Conference (GLOBECOM)

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Resistive memories are considered a promising memory technology enabling high storage densities with inmemory computing capabilities. However, the readout reliability of resistive memories is impaired due to the inevitable existence of wire resistance, resulting in the sneak path problem. Motivated by this problem, we study polar coding over channels with different reliability levels, termed non-stationary polar codes, and we propose a technique improving its bit error rate (BER) performance. We then apply the framework of non-stationary polar codes to the crossbar array and evaluate its BER performance under two modeling approaches, namely binary symmetric channels (BSCs) and binary asymmetric channels (BSCs). Finally, we propose a technique for biasing the proportion of high-resistance states in the crossbar array and show its advantage in reducing further the BER. Several simulations are carried out using a SPICE-like simulator, exhibiting significant reduction in BER.

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Section: Introductionmentioning

confidence: 93%

Section: Application To Resistive Crossbar Arrays a General Framentioning

confidence: 99%

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Non-Stationary Polar Codes for Resistive Memories

Zorgui

Fouda²,

Wang³

et al. 2019

2019 IEEE Global Communications Conference (GLOBECOM)

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“…The wire resistance is inevitable in nanostructure crossbar arrays. It is expected that the wire resistance would reach around 90Ω for 5nm feature size [35]. The wire resistance creates undesired IR voltage drops that accumulate across the columns in the array leading to unwanted paths between the input and output nodes.…”

Section: Inevitable Wire Resistance Problem In Crossbar Structuresmentioning

confidence: 99%

IR-QNN Framework: An IR Drop-Aware Offline Training of Quantized Crossbar Arrays

Fouda

Lee

et al. 2020

IEEE Access

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“…We perform systematic simulations on 4 parameters; On/Off ratio, line-resistance (Rline), array size, and weight pattern (for (a) random and (b) trained by the popular Softmax function often used in machine-learning algorithms) as shown in Figure 6-3. From the reported articles, device On/Off ratio varies from 2 to 100 for analog memristor operation [36], [51], [91]- [98] and the line resistance Rline can be up to 10Ω for nanoscale devices [90], [99]- [104]. In the simulation, randomized input patterns are applied and we show the resulting error of the last column, since it will experience stronger series resistance effects (worst case).…”

Section: Array Operation Conditions and Parasitic Effectsmentioning

confidence: 99%