Modeling and characterization of 80 V LDMOSFET for RF communications

Abstract

This paper presents the design and optimization of a 80V LDMOSFET used in RF power amplifiers for cellular base station applications. SRP data from an experimantal device was used to prototype the device using advanced 2-D process and device simulators. DC and RF characterization has been performed for the device. A proper match has been obtained between the measured and simulated data. A simple circuit model has been developed in which each of the components has been associated with the physical principles of device operation. A close match between the measured and modeled RF data has been reported. NOMENCLATURE LDD Lightly doped drain R ,On-resistance (Q) R , , Specific on-resistance (mncm') g ,Input capacitance (pF) Cos, Output capacitance (pF) C ,ss P, Total input power (W) Po,, Total output power (W) s11, s22 S Parameters I NTRO D U CTlO N Miller feed backcapacitance( p F)Recent surge in the personal communications services in the L-band has created a huge demand for cost-effective, high performance RF subsystems. The key requirement for the realization of such systems is the design and development of highly linear, high gain transistors. Silicon technology has evolved to meet this demand with the development of LDMOS device structures that have proven to be highly efficient for these applications [l-3].The RF performance of these devices is mainly determined b y the inherent parasitics of the device. An in-depth understanding of device physics helps to predict the origin of these parasitics and hence means to reduce them. In this investigation, the device structure is represented in the form of a 2-D grid, and device simulations are performed to solve the semiconductor equations at all the points in the grid [4]. Second order effects such as high-field transport and heat generation and diffusion are also included.In this work, extensive DC simulations were performed on an LDMOSFET structure to study the static behavior of the device, and the simulation results were compared with the measured data. A simple and compact circuit model was developed b y extracting the model parameters from measured and simulated data. This circuit model was then used to perform the RF characterization of the device. The circuit model has been validated b y comparing the simulated RF data with the measured data. Fig.1 shows the basic device structure. The device is fabricated on a 0.02 SZ-cm ptype substrate on which a 9 pm thick ptype epitaxial region (9 Q-cm) was grown at 1000°C. A p-type sinker diffusion was used to ground the source to substrate in order to minimize the common lead inductance and improve RF gain. Doping profiles available from SRP data were used to generate the device structure. The pbody region under the gate forms the channel. 0-7803-3916-9/97/$5.00 01 997 IEEE 92 DEVICE STRUCTURE

A Physically-Based Compact Model for LDMOS Transistors

“…The two most relevant effects in LDMOS is the sharp peaking of the transconductance (g m ) at threshold and the increase of the gate-to-drain capacitance well below threshold (section 6). Previous LDMOS models assume uniform lateral channel and thus can not reproduce such effects [3]. In this work, the channel model is a physically based graded channel charge sheet model GCIM (Graded Channel IGFET Model) which is implemented in Motorola's simulator MCSPICE [4].…”