Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations in 32-nm node standard cell

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

“…The Ebd that represents the post-patterned breakdown field decreased with increasing temperature. The overall effect of the location of the contacts related to the gate on the main MOSFET performances-drive current and leakage-was studied by [13,15,16,28,29] and found to mostly depend on three main parameters ( Figure 11): The overall effect of the location of the contacts related to the gate on the main MOSFET performances-drive current and leakage-was studied by [13,15,16,28,29] and found to mostly depend on three main parameters ( Figure 11): The overall effect of the location of the contacts related to the gate on the main MOSFET performances-drive current and leakage-was studied by [13,15,16,28,29] and found to mostly depend on three main parameters ( Figure 11 (1) The distance of S/D contacts to related gate: the larger the distance of the contacts from the gate, the lower is the effective relaxation they induce into the stressed layer [30]. In most cases, stress enhance techniques for the nMOSFET used a tensile stressed liner made of nitride that also used as the soft contact etch stop layer (cESL).…”

“…A simple threshold limit could be defined based on two conditions: N and Z, in which N is the number of nearby contacts that interact with the area defined by the contact under analysis (CUA) sized-up by Z. For example, at 28 nm, that CS.W.1/CS.S.1 = 0.04/0.07 μm [15,16], we can assume N ≥ 3, and Z ≈ 2 × CS.S.1 = 0.14 um. However, exact values for N and Z should be set experimentally, as they have a strong dependence on the process conditions that set up the optical range.…”

“…Smaller value of contact increases contact resistance, as well as the contact resistance distribution. (left) Data of 130~90 nm technology and (right) data analysis of 28 nm technology based on[15].…”

Critical dimension uniformity and contact edge roughness in extreme ultraviolet lithography: effect of photoacid generator, sensitizer and quencher

“…[2][3][4][5][6][7] Furthermore, the sidewall roughness of single contacts [usually called contact edge roughness (CER)] has various effects on transistor performance such as the time-dependent dielectric breakdown coming from the reduction of the space between the contacts and gate in a transistor and the saturation value of source/drain current. 11 The increased importance of contact roughness and variability issues demands first for a reliable and advanced measurement and characterization approach [8][9][10][11][12][13] and second, for systematic experimental and modeling studies investigating the CD variation and CER dependencies on various EUV resist properties and process conditions. 11 The increased importance of contact roughness and variability issues demands first for a reliable and advanced measurement and characterization approach [8][9][10][11][12][13] and second, for systematic experimental and modeling studies investigating the CD variation and CER dependencies on various EUV resist properties and process conditions.…”

Contact edge roughness in EUV lithography

“…Summing the contributions from all slices to the S/D saturation current, the following formula is obtained: HSPICE simulation (conventional) [130]. In a conventional circuit simulation, the contact area is considered which is directly related to the contact resistance by dividing the contact resistivity by the contact area.…”