Modeling and Characterizing Power Variability in Multicore Architectures

Meng, Ke; Huebbers, Frank; Joseph, Russ; Ismail, Yehea

doi:10.1109/ispass.2007.363745

Cited by 11 publications

(3 citation statements)

References 45 publications

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“…While conceptually simple, lock-step becomes an increasing burden as device scaling continues [16]. As technology scaling continues to concern the performance and power consumption overheads, multi-core designs are being investigated to keep up with Moore's Law [17]. The increase in the integration of a number of processor cores on a single chip makes the chip more dense in area and hence making them more vulnerable to reliability threats such as soft errors.…”

Section: Related Workmentioning

confidence: 99%

UnSync: A Soft Error Resilient Redundant Multicore Architecture

Jeyapaul

Hong

Rhisheekesan

et al. 2011

2011 International Conference on Parallel Processing

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Abstract-Reducing device dimensions, increasing transistor densities, and smaller timing windows, expose the vulnerability of processors to soft errors induced by charge carrying particles. Since these factors are only consequences of the inevitable advancement in processor technology, the industry has been forced to improve reliability on general purpose Chip Multiprocessors (CMPs). With the availability of increased hardware resources, redundancy based techniques are the most promising methods to eradicate soft error failures in CMP systems. In this work, we propose a novel redundant CMP architecture (UnSync) that utilizes hardware based detection mechanisms (most of which are readily available in the processor), to reduce overheads during error free executions. In the presence of errors (which are infrequent), the always forward execution enabled recovery mechanism provides for resilience in the system. We design a detailed RTL model of our UnSync architecture and perform hardware synthesis to compare the hardware (power/area) overheads incurred. We compare the same with those of the Reunion technique, a state-of-the-art redundant multi-core architecture. We also perform cycle-accurate simulations over a wide range of SPEC2000, and MiBench benchmarks to evaluate the performance efficiency achieved over that of the Reunion architecture. Experimental results show that, our UnSync architecture reduces power consumption by 34.5% and improves performance by up to 20% with 13.3% less area overhead, when compared to Reunion architecture for the same level of reliability achieved.

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Section: Related Workmentioning

confidence: 99%

UnSync: A Soft Error Resilient Redundant Multicore Architecture

Jeyapaul

Hong

Rhisheekesan

et al. 2011

2011 International Conference on Parallel Processing

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“…All transistors within a section are assumed to have identical parameter variation. Several methods, including hierarchical methods [28] as well as convolution kernels [29], have been used to assign parameter deviations to neighboring blocks. An alternative to Monte Carlo simulation is to model systematic components of leakage variation through an empirically derived gate length deviation model [30].…”

Section: Variation Under Statistical Distributionsmentioning

confidence: 99%

Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors

et al. 2007

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Power is the source of the greatest problems facing microprocessor designers. High-power processors rapidly deplete battery energy. Rapid changes in power consumption result in on-chip voltage fluctuations that bring transient errors. High spatial and temporal power densities bring high temperatures, which result in decreased lifetime reliability. High temperatures also increase leakage power consumption, thereby closing a self-reinforcing powertemperature feedback loop. The effects of increasing power consumption, power variation, and power density are expensive and distasteful. The wages of power are bulky short-lived batteries, huge heatsinks, large on-die capacitors, high server electric bills, and unreliable microprocessors. The only alternative is optimizing microprocessor power consumption, temperature, and reliability. However, this depends on accurate modeling and rapid analysis of properties that span different disciplines and levels, from device physics, to numerical methods, to microarchitectural design. This article surveys the most important problems brought directly and indirectly by power consumption, indicates the relationships among them, explains recent methods of efficiently modeling them, and indicates promising directions in the ongoing fight against power.

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“…Transistor-level simulators [11] incorporating these models can accurately predict leakage; however, they are computationally expensive as a result of iteratively solving complex leakage formulas. Furthermore, statistical leakage analysis techniques [12] should be adopted due to the increasing process variation phenomena in the nanoscale CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

Temperature-Aware Leakage Estimation Using Piecewise Linear Power Models

Liu

Yang

2010

IEICE Trans. Electron.

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Due to the superlinear dependence of leakage power consumption on temperature, and spatial variations in on-chip thermal profiles, methods of leakage power estimation that are known to be accurate require detailed knowledge of thermal profiles. Leakage power depends on the integrated circuit (IC) thermal profile and circuit design style. Here, we show that piecewise linear models can be used to permit accurate leakage estimation over the operating temperature ranges of the ICs. We then show that for typical IC packages and cooling structures, a given amount of heat introduced at any position in the active layer will have a similar impact on the average temperature of the layer. These two observations support the proof that, for wide ranges of design styles and operating temperatures, extremely fast, coarse-grained thermal models, combined with piecewise linear leakage power consumption models, enable the estimation of chip-wide leakage power consumption. These results are further confirmed through comparisons with leakage estimates based on detailed, time-consuming thermal analysis techniques. Experimental results indicate that, when compared with a leakage analysis technique that relies on accurate spatial temperature estimation, the proposed technique yields a 59,259× to 1,790,000× speedup in estimating leakage power consumption, while maintaining accuracy.

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Modeling and Characterizing Power Variability in Multicore Architectures

Abstract: Abstract

Cited by 11 publications

References 45 publications

UnSync: A Soft Error Resilient Redundant Multicore Architecture

UnSync: A Soft Error Resilient Redundant Multicore Architecture

Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors

Temperature-Aware Leakage Estimation Using Piecewise Linear Power Models

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