Modeling and Energy Optimization of LDPC Decoder Circuits With Timing Violations

Leduc-Primeau, François; Kschischang, Frank R.; Gross, Warren J.

doi:10.1109/tcomm.2017.2778247

Cited by 12 publications

(21 citation statements)

References 42 publications

(59 reference statements)

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“…We will model deviations occurring in a QS LDPC decoder by using the approach proposed in [6], where the dependence on the circuit's state is replaced with a dependence on the statistical distribution of the input, yielding a memoryless model that is nonetheless accurate. Since we are usually interested in the progress made by the decoder from one iteration to the next, we can summarize the effect of deviations on the decoder by considering that every message ν .…”

Section: A Deviation Modelmentioning

confidence: 99%

“…In this paper, we use a deviation modeling approach proposed in [6] that can generate accurate memoryless deviation models of QS circuits, and show how this deviation model can be used to predict the performance and energy consumption of a QS decoder operating on a finite-length code. Two approaches can be used to predict the error correction performance.…”

Section: Introductionmentioning

confidence: 99%

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Finite-length quasi-synchronous LDPC decoders

Leduc-Primeau

Gross

2016

2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC)

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Quasi-synchronous systems aim to reduce energy consumption by allowing timing violations in a synchronous circuit, while performance guarantees are provided by analyzing the system with a suitable deviation model. This paper studies the performance of quasi-synchronous LDPC decoders for regular codes of finite length. We present an approach to accurately predict the decoding performance and energy consumption of the decoder for a specific average channel quality and maximum number of iterations. These analytical results are then compared with gate-level circuit simulations of a quasi-synchronous decoder.

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Section: A Deviation Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Finite-length quasi-synchronous LDPC decoders

Leduc-Primeau

Gross

2016

2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC)

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“…We characterize the effect of timing violations on the algorithm by studying small test circuits that can be simulated quickly, using the same approach as in [37]. In the proposed architecture, the same processing circuit can be replicated several times to form each layer, depending on the required degree of parallelism.…”

Section: Quasi-synchronous Implementationsmentioning

confidence: 99%

VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing

Ardakani

Leduc-Primeau

Onizawa

et al. 2017

IEEE Trans. VLSI Syst.

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209

109

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The hardware implementation of deep neural networks (DNNs) has recently received tremendous attention: many applications in fact require high-speed operations that suit a hardware implementation. However, numerous elements and complex interconnections are usually required, leading to a large area occupation and copious power consumption. Stochastic computing has shown promising results for low-power area-efficient hardware implementations, even though existing stochastic algorithms require long streams that cause long latencies. In this paper, we propose an integer form of stochastic computation and introduce some elementary circuits. We then propose an efficient implementation of a DNN based on integral stochastic computing. The proposed architecture has been implemented on a Virtex7 FPGA, resulting in 45% and 62% average reductions in area and latency compared to the best reported architecture in literature. We also synthesize the circuits in a 65 nm CMOS technology and we show that the proposed integral stochastic architecture results in up to 21% reduction in energy consumption compared to the binary radix implementation at the same misclassification rate. Due to fault-tolerant nature of stochastic architectures, we also consider a quasi-synchronous implementation which yields 33% reduction in energy consumption w.r.t. the binary radix implementation without any compromise on performance.

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“…Note that our model assumes constant voltage. Non-trivial results that show how real energy gains can occur by lowering voltages in decoder circuits have been studied in [22], but we do not study this here.…”

Section: Other Energy Models Of Computationmentioning

confidence: 99%

Energy, Latency, and Reliability Tradeoffs in Coding Circuits

Blake

Kschischang

2019

IEEE Trans. Inform. Theory

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It is shown that fully-parallel encoding and decoding schemes with asymptotic block error probability that scales as O (f (n)) have Thompson energy that scales as Ω ln f (n)n . As well, it is shown that the number of clock cycles (denoted T (n)) required for any encoding or decoding scheme that reaches this bound must scale as T (n) ≥ ln f (n). Similar scaling results are extended to serialized computation. The Grover information-friction energy model is generalized to three dimensions and the optimal energy of encoding or decoding schemes with probability of block error Pe is shown to be at least Ω n (ln Pe (n)) 1 3 .. This approach is generalized to serial implementations. Recent work on the energy complexity of good decoding has focused largely on planar circuits. However, circuits implemented in three-dimensions exist [6], and so we generalize the recent information friction (or bit-meters) model introduced by Grover in [3] to circuits implemented in three-dimensions and extend the technique of Grover to show that, in terms of block length n, a bit-meters coding scheme in which block error probability is given by P e (n) has encoding/decoding energy that scales as Ω n (ln P e (n)) 1 3. We show how this approach can be generalized to an arbitrary number of dimensions. In Section II we discuss prior work, and in particular we discuss existing results on complexity lower bounds for different models of computation for different notions of "good" encoders and decoders. The main technical results of this work are in Section III, where we study the Thompson energy model, and in Section IV, where we study a multi-dimensional generalization of the Grover bit-meters model. In these sections we present lower bounds for decoders, as the derivation for encoding lower bounds is almost exactly the same. We provide an outline of the technique for encoder lower bounds in Section V. In Section VI we discuss limitations and weaknesses in the model used. In Section VII, we discuss other energy models of computation.

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Modeling and Energy Optimization of LDPC Decoder Circuits With Timing Violations

Cited by 12 publications

References 42 publications

Finite-length quasi-synchronous LDPC decoders

Finite-length quasi-synchronous LDPC decoders

VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing

Energy, Latency, and Reliability Tradeoffs in Coding Circuits

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