Modeling Attacks on PUF

Santikellur, Pranesh; Chakraborty, Rajat Subhra

doi:10.1007/978-981-19-4017-0_4

Cited by 10 publications

(19 citation statements)

References 11 publications

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“…It emphasizes the need for protocols to be robust enough. Recent research focus on using Deep Learning (DL) [117], [118], genetic programming [119], and Artificial Neural Networks (ANN) [120], [121] based techniques to model the design with reduced error and improved prediction accuracy of 64-bit and 128-bit CRPs.…”

Section: Mathematical Modeling Of Lspufmentioning

confidence: 99%

“…Furthermore, obtaining CRPs is found indeed successful using SCA [124] and cryptanalysis [96]. [117] uses the gradient-based numerical optimization method to model the iPUF (4,4) with a training time of 5.23 minutes. This method uses the knowledge of parity vectors obtained from the challenge.…”

Section: H Modeling Attack On Lspufmentioning

confidence: 99%

“…Probably Approximately Correct (PAC) [140], the sub-space pre-learning method [141] uses randomness and known CRPs to model the iPUF. The uniformity metric is found helpful in splitting the iPUF (4,4) [50], [117] applying LR. The latest technique employs the splitting attack [114] using the divide and conquer ML algorithm for 64-bit iPUF (8,8), and (1,9) with a training size ranging between 300 million to 750 million CRPs, and the prediction accuracy was near 95%.…”

Section: H Modeling Attack On Lspufmentioning

confidence: 99%

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Arbiter PUF—A Review of Design, Composition, and Security Aspects

Hemavathy

Bhaaskaran

2023

IEEE Access

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Hardware security modules play a crucial role in protecting and preserving technologically integrated systems that are used in daily life. They employ cryptographic protocols to secure a system against adversaries. Generally, cryptographic algorithms and security keys are quintessential for maintaining the security of a system. Cryptography uses a secret key to encipher and decipher the data. These secret keys are stored in a non-volatile memory that attackers can easily access. The hardware security primitive, Physical Unclonable Function (PUF) is a promising alternative for enhancing the security of interconnected devices. A PUF produces an output in response to an input based on physical structure and intrinsic manufacturing variations of an integrated circuit (IC). The generated random response being unpredictable, act as a robust secret key in cryptographic protocols. The first silicon PUF is the Arbiter PUF, which can instantly produce significantly more secret keys based on the input with a lightweight design. Due to its advantage, it is best suited for device authentication in resource-constrained applications employing the Internet of Things (IoT). The PUF is also suitable for applications such as the Internet of Vehicles, the Internet of Medical Things, RFID tags, and smart cards. In this paper, the basic Arbiter PUF design is implemented in ZedBoard to analyze the PUF performance characteristics for 16, 32, and 64-bit responses. A review of Arbiter PUF design, different compositions of Arbiter PUF, their individual characteristics, and vulnerabilities against machine-learning attacks have been presented at their broader best in this paper.

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Section: Mathematical Modeling Of Lspufmentioning

confidence: 99%

Section: H Modeling Attack On Lspufmentioning

confidence: 99%

Section: H Modeling Attack On Lspufmentioning

confidence: 99%

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Arbiter PUF—A Review of Design, Composition, and Security Aspects

Hemavathy

Bhaaskaran

2023

IEEE Access

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“…That is, an adversary can mimic the PUF by building a mathematical model using a small number of CRPs. We note that several successful attacks have been reported in the literature against the APUF architectures [23], [24], [25], [26], [27], [28], [29]. To improve the robustness of APUF against classical ML based modeling attacks, an XOR APUF was proposed in [5] to XOR the multiple APUFs outputs, all having the same challenge input.…”

Section: Introductionmentioning

confidence: 99%

“…However, hardware cost of XOR PUF as well as the percentage of unstable responses exponentially increase with the increasing number of APUF components in an XOR PUF [31]. Moreover, in recent years, different variants of the modeling attacks have been reported to break XOR PUF architectures when given sufficient CRPs [23], [24], [25], [26], [29], [30], [31], [32], [33]. Several approaches have been introduced that utilize pre-extracted delay parameters to improve the security of XOR APUFs [32], [34], [35].…”

Section: Introductionmentioning

confidence: 99%

Implementation of Efficient XOR Arbiter PUF on FPGA With Enhanced Uniqueness and Security

2022

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Physically unclonable functions (PUFs) are recently utilized as a promising security solution for authentication and identification of internet of things (IoT) devices. In this article, we present an efficient implementation of XOR Arbiter PUF (XOR APUF) on field-programmable gate arrays (FPGAs). In our work, we incorporated concept of discrete programmable delays logic (PDL) configurations, the obfuscated challenges and temporal majority voting (TMV) before the XOR operation concurrently to enhance uniqueness and security. The derived design has been verified on 25 Xilinx Artix-7 FPGAs and the results are promising with uniqueness of 48.69%, uniformity 50.73% and reliability 99.41%, which significantly improves over previous work into XOR APUF designs. In addition, we also investigate modeling attack resistance of the proposed design against various modelling attacks and the security analysis show that the proposed PUF has lower prediction rate (< 65%) when compared to the previous XOR APUF designs.INDEX TERMS Physical unclonable functions (PUFs), Internet of Things (IoT), programmable delays line (PDL), FPGA, XOR arbiter PUF (XOR APUF).

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Secure Dynamic PUF for IoT Security

Rajput,

Dofe

2023

IFIP Advances in Information and Communication Technology

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Modeling Attacks on PUF

Cited by 10 publications

References 11 publications

Arbiter PUF—A Review of Design, Composition, and Security Aspects

Arbiter PUF—A Review of Design, Composition, and Security Aspects

Implementation of Efficient XOR Arbiter PUF on FPGA With Enhanced Uniqueness and Security

Secure Dynamic PUF for IoT Security

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