2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS) 2016
DOI: 10.1109/rtas.2016.7461342
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Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems

Abstract: Abstract-Manycore chips are a promising computing platform to cope with the increasing performance needs of critical realtime embedded systems (CRTES). However, manycores adoption by CRTES industry requires understanding task's timing behavior when their requests use manycore's network-on-chip (NoC) to access hardware shared resources. This paper analyzes the contention in wormhole-based NoC (wNoC) designs -widely implemented in the high-performance domain -for which we introduce a new metric: worst-contention… Show more

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Cited by 16 publications
(76 citation statements)
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“…Routers are pipelined and consist of 4 stages: input buffer, routing, switch allocation, and crossbar traversal. In line with other works [19], [18] in all wNoC setups we use single-flit packets only to improve performance guarantees. The number of VCs is 1.…”
Section: B Reducing Contention In Probabilistic Wnocsmentioning
confidence: 62%
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“…Routers are pipelined and consist of 4 stages: input buffer, routing, switch allocation, and crossbar traversal. In line with other works [19], [18] in all wNoC setups we use single-flit packets only to improve performance guarantees. The number of VCs is 1.…”
Section: B Reducing Contention In Probabilistic Wnocsmentioning
confidence: 62%
“…Upper-bounding latency deterministically only requires forcing all wNoC requests to experience the worst-possible delay [19]. To illustrate probabilistic upperbounding, let us assume a hardware resource whose analysistime latency can be 1 or 2 cycles with the same probability: etd a =< (1, 2) , (0.5, 0.5) > where the first vector corresponds to the different latencies and the second to their associated probabilities.…”
Section: Upper-bounding Contention In Probabilistic Wnocsmentioning
confidence: 99%
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