Modeling in Verilog-AMS of a front-end for the design of a multichannel readout ASIC for Si microstrips

Montiel, Andreu; Casanova, R.; Diéguez, A.

doi:10.1109/smacd.2012.6339442

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Mixed-signal Simulation1

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2021

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“…The models are later replaced by components which are described at transistor level or netlist level as the component designs are finalized. Using models on different abstraction levels allows the newly designed components to be verified as part of the whole system already in the early stages of the chip design [9][10][11][12].…”

Section: Mixed-signal Simulationmentioning

confidence: 99%

High level verification of the VFAT3 ASIC for CMS GEM detectors

Petrow¹,

Aspell²,

Ciaglia³

et al. 2021

J. Inst.

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A front-end readout chip VFAT3 was designed for the muon detector gas electron multipliers (GEM). GEMs were installed at the Compact Muon Solenoid (CMS) experiment of the Large Hadron Collider (LHC) at CERN for the high luminosity upgrade. The design of the VFAT3 uses 790 analog and 172 digital blocks which are highly integrated, thus it is crucial to ensure that the different blocks work together and the chip works as a whole. Mixed signal simulation methods were used to verify the high level functionality. Trigger latencies of 125, 150, 175 and 225 ns were found for front-end peaking times of 25, 50, 75 and 100 ns, respectively. The maximum trigger rate for reading out standard data packets was found to be 1.7 MHz. Results of the VFAT3 high level verification are presented and the simulation methods described.

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Section: Mixed-signal Simulationmentioning

confidence: 99%