Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting

Abstract

Today's Application Specific Instruction-set Processor (ASIP) design methodology often employs centralized Architecture Description Language (ADL) processor models, from which software tools, such as C compiler, assembler, linker, and instruction-set simulator, can be automatically generated. Among these tools, the C compiler is becoming more and more important. However, the generation of C compilers requires high-level architecture information rather than low-level details needed by simulator generation. This makes it particularly difficult to include different aspects of the target architecture into one single model, and meanwhile keeping consistency. This paper presents a modeling style, which is able to capture high-and low-level architectural information at the same time and make it possible to drive both the C compiler and the simulator generation without sacrificing the modeling flexibility. The proposed approach has been successfully applied to model a number of contemporary, real-world processor architectures.

C Compilers for ASIPs

“…Thus, in order to close the semantic gap, a new SEMANTICS section is introduced to LISA [126]. It captures the instruction behavior at a higher abstraction level while ignoring all structural details like pipelining for instance.…”