Modeling of apparent activation energy and lifetime estimation in NAND flash memory

Lee, Kyunghwan; Kang, Myounggon; Hwang, Yoohwa; Shin, Hyungcheol

doi:10.1088/0268-1242/30/12/125006

Cited by 5 publications

(2 citation statements)

References 20 publications

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“…Furthermore, it been reported that lateral charge transport in the conduction band of the nitride layer is responsible for non-Arrhenius retention [19,20]. The thermal emission and lateral transport are faster than the tunneling charge loss and thus the data retention time is dependent on temperature [21,22]. In this experiment, the ratio for the dielectric recovery using delayed pulse, temperature, and time were calculated from the universal unified detrapping matrix equation [3].…”

Section: Resultsmentioning

confidence: 98%

Reduction of interface traps between poly-Si and SiO₂ layers through the dielectric recovery effect during delayed pulse bias stress

et al. 2017

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We investigate the interface trap behavior between tunneling oxide and poly-Si channel layer post erase/write cycling with a delayed pulse by using deep level transient spectroscopy. For comparison of the defect states depending on the stress pulses, a Schottky and a metal-oxide semiconductor device were fabricated. A defect state at about E -0.51 eV in the Schottky device was measured before the annealing process. Three-hole trap states with activation energies of E +0.28 eV, E +0.53 eV, and E +0.76 eV appeared after the post-annealing process. The electron trap was about E -0.15 eV after erase/write 3000 cycling was applied at ±10 V for 100 ms at 25 °C and 85 °C. These defect states may have an effect on the charge loss behavior of the electrons localized in the charge trap layer at the retention mode of three-dimensional non-volatile memory devices. Dramatically, after the endurance stress was applied with a delayed pulse of 300 cycling at 85 °C for 50.4 h, no interface traps of the deep level transient spectroscopy spectra appeared. Dielectric recovery can decrease the density of the interface trap and improve the retention properties. This may have been caused by the passivation effect on the dangling bond of the interface traps.

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Section: Resultsmentioning

confidence: 98%

Reduction of interface traps between poly-Si and SiO₂ layers through the dielectric recovery effect during delayed pulse bias stress

et al. 2017

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“…Lee et al [26] studied E aa for sub 20nm NAND flash memory. They revealed the anomalous origin feature at E aa (apparent activation energy) and derived the mathematical formula which is a function of E a (the interface trap) in NAND flash, and used the proposed mathematical equation to estimate the lifetime of the NAND flash.…”

Section: B Model-based Techniques For Optimizing Reliability Of Nand Flash Memorymentioning

confidence: 99%

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory

Zhang

et al. 2019

IEEE Access

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NAND flash memory is widely used in various computing systems. However, flash blocks can sustain only a limited number of program/erase (P/E) cycles, which are referred to as the endurance. On one hand, in order to ensure data integrity, flash manufacturers often define the maximum P/E cycles of the worst block as the endurance of flash blocks. On the other hand, blocks exhibit large endurance variations, which introduce two serious problems. The first problem is that the error correcting code (ECC) is often over-provisioned, as it has to be designed to tolerate the worst case to ensure data integrity, which causes longer decoding latency. The second problem is the underutilized block's lifespan due to conservatively defined block endurance. Raw bit error rate (RBER) of most blocks have not arrived the allowable RBER based on the nominal endurance point, which implies that the conventional P/E cycle-based block retirement policies may waste large flash storage space. In this paper, to exploit the storage capacity of each flash block, we propose an RBER-aware lifetime prediction scheme based on machine learning technologies. We consider the problem that the model can lose prediction effectiveness over time and use incremental learning to update the model for adapting the changes at different lifetime stages. At run time, trained data will be gradually discarded, which can reduce memory overhead. For evaluating our purpose, four wellknown machine learning techniques have been compared in terms of predictive accuracy and time overhead under our proposed lifetime prediction scheme. We also compared the predicted values with the tested values obtained in the real NAND flash-based test platform, and the experimental results show that the support vector machine (SVM) models based on our proposed lifetime prediction scheme can achieve as high as 95% accuracy for flash blocks. We also apply our proposed lifetime prediction scheme to predict the actual endurance of flash blocks at four different retention times, and the experimental results show that it can significantly improve the maximum P/E cycle of flash blocks from 37.5% to 86.3% on average. Therefore, the proposed lifetime prediction scheme can provide a guide for block endurance prediction.

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Reliability Analysis by Charge Migration of 3D SONOS Flash Memory

Jeong

Sung

Yang

et al. 2020

2020 IEEE International Reliability Physics Symposium (IRPS)

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Modeling of apparent activation energy and lifetime estimation in NAND flash memory

Cited by 5 publications

References 20 publications

Reduction of interface traps between poly-Si and SiO₂ layers through the dielectric recovery effect during delayed pulse bias stress

Reduction of interface traps between poly-Si and SiO₂ layers through the dielectric recovery effect during delayed pulse bias stress

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory

Reliability Analysis by Charge Migration of 3D SONOS Flash Memory

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Modeling of apparent activation energy and lifetime estimation in NAND flash memory

Cited by 5 publications

References 20 publications

Reduction of interface traps between poly-Si and SiO2 layers through the dielectric recovery effect during delayed pulse bias stress

Reduction of interface traps between poly-Si and SiO2 layers through the dielectric recovery effect during delayed pulse bias stress

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory

Reliability Analysis by Charge Migration of 3D SONOS Flash Memory

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Product

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Reduction of interface traps between poly-Si and SiO₂ layers through the dielectric recovery effect during delayed pulse bias stress

Reduction of interface traps between poly-Si and SiO₂ layers through the dielectric recovery effect during delayed pulse bias stress