Reduction of interface traps between poly-Si and SiO₂ layers through the dielectric recovery effect during delayed pulse bias stress

Abstract

We investigate the interface trap behavior between tunneling oxide and poly-Si channel layer post erase/write cycling with a delayed pulse by using deep level transient spectroscopy. For comparison of the defect states depending on the stress pulses, a Schottky and a metal-oxide semiconductor device were fabricated. A defect state at about E -0.51 eV in the Schottky device was measured before the annealing process. Three-hole trap states with activation energies of E +0.28 eV, E +0.53 eV, and E +0.76 eV appeared after the post-annealing process. The electron trap was about E -0.15 eV after erase/write 3000 cycling was applied at ±10 V for 100 ms at 25 °C and 85 °C. These defect states may have an effect on the charge loss behavior of the electrons localized in the charge trap layer at the retention mode of three-dimensional non-volatile memory devices. Dramatically, after the endurance stress was applied with a delayed pulse of 300 cycling at 85 °C for 50.4 h, no interface traps of the deep level transient spectroscopy spectra appeared. Dielectric recovery can decrease the density of the interface trap and improve the retention properties. This may have been caused by the passivation effect on the dangling bond of the interface traps.

Improving Bias-Stress Stability of p-Type Organic Field-Effect Transistors by Constructing an Electron Injection Barrier at the Drain Electrode/Semiconductor Interfaces

“…The extracted σ h was used as the initial parameter to fit the I SD decay curves. Besides, for the SiO 2 -interfacial trap states, S n = ∼10 –19 cm 2 , S p = ∼10 –27 cm 2 , and N t = ∼10 13 cm –3 are taken into account as the initial parameters based on the data in refs − . As shown in Figure S9, the rate eq provided a thorough fit to the normalized I SD decay curves.…”

Impacts of extra charges on trap level modulations atcSi/aSiO2interface: correlations to leakage current recovery in oxide dielectric

“…It is widely accepted that the trap level modulation originates from the lattice variation after the structure relaxation at different charging systems [30][31][32]. Dielectric degradation can also be described by the charge trapping/detrapping process [30,[33][34][35][36] on the basis of the Marcus theory, which was successfully applied to the interfaces of Si/SiO 2 and Si/SiO 2 /high-k stacks [37][38][39].…”

“…Finally, we summarized a table that includes recent study on SILC dielectric recovery methods and non-recovery results, and make a grouping by our observed simulation results, shown in table 1. Tunneling oxide degradation; [32] Forming induced oxygen vacancies; [49] Electron accumulation; defect at interface;…”