Modeling of Drain Electric Flux Passing Through the BOX Layer in SoI MOSFETs—Part I: Preparation for Modeling Based on Conformal Mapping

Abstract

Silicon-on-insulator (SoI) technology has been reported as a technique to improve electrical characteristics over those of bulk MOSFETs. However, this approach results in the disadvantage of increased drain-induced barrier lowering (DIBL) due to drain electric flux (or field) passing through the buried oxide (BOX) layer. Against such a background, the development of a method to easily estimate the amount of this electric flux is expected to support the prediction of BOX-related DIBL. This paper involved the investigation of a model-derived analytically using conformal mapping techniques to represent the amount of flux in subthreshold regions of ground-plane SoI MOSFETs. To create the model, this paper was divided into two parts. In Part I, as preparation for model development, the relationships between coordinates in MOSFETs and potential/stream function were derived using conformal mapping, and related validity was verified. In Part II, the model's development was considered based on these relationships, and its validity was also verified.Index Terms-Buried oxide (BOX), conformal mapping, drain-induced barrier lowering (DIBL), electric field, electric flux, parasitic capacitance, relative permittivity, short channel effect, silicon on sapphire, silicon-on-insulator (SoI) technology.