Modeling of laser-annealed polysilicon TFT characteristics

Armstrong, G.A.; Uppal, S.; Brotherton, S. D.; Ayres, J. R.

doi:10.1109/55.596923

Cited by 63 publications

(31 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Although there has been research to analyze the grain-boundary in poly-Si TFTs, [26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41] this article analyzes the dependence on the grain-boundary location, following a brief report by the authors. 42 Figure 1 shows the structure of a poly-Si TFT for twodimensional ͑2D͒ device simulation.…”

Section: Introductionmentioning

confidence: 99%

Dependence of polycrystalline silicon thin-film transistor characteristics on the grain-boundary location

Kimura

Inoue

Shimoda

et al. 2001

Journal of Applied Physics

View full text Add to dashboard Cite

Dependence of transistor characteristics on the grain-boundary location in polycrystalline silicon (poly-Si) thin-film transistors (TFTs) has been analyzed using device simulation. In the linear region, degradation is similar wherever the grain boundary is located. On the other hand, in the saturation region, degradation is less when the grain boundary is in the pinch-off region near the drain edge and degradation is similar when the grain boundary is elsewhere. Although this dependence is similar to the dependence on the trap location in single-crystal silicon transistors, the mechanism is different. This dependence in poly-Si TFTs is because the coulombic potential barrier caused by the grain boundary is lowered in the high electric field in the pinch-off region. This is a kind of Poole–Frenkel effect.

show abstract

Section: Introductionmentioning

confidence: 99%

Dependence of polycrystalline silicon thin-film transistor characteristics on the grain-boundary location

Kimura

Inoue

Shimoda

et al. 2001

Journal of Applied Physics

View full text Add to dashboard Cite

show abstract

“…In the case of ALD and sputtered films, annealing can also reduce oxygen deficiency of as-grown films and improve crystal quality. Postgrowth annealing has a similar effect on nc-ZnO films as laser annealing has on poly-Si thin films [49][50][51]. The highest current density obtained was 800 mA/mm for 2 µ m gate length PLD ZnO devices.…”

Section: Performance Optimizationmentioning

confidence: 77%

Self-assembled nanocrystalline ZnO thin film transistor performance optimization for high speed applications

Bayraktaroglu¹,

Leedy²

2014

Turk J Phys

View full text Add to dashboard Cite

Abstract:ZnO nanocrystals grown at relatively low temperatures using various vacuum deposition techniques can yield semiconducting thin films of self-assembled nanocolumns 20-50 nm in diameter. Such films are suitable for the fabrication of high speed and transparent thin film transistors (TFTs). Unlike amorphous TFTs, the performance of ZnO transistors depends both on the crystal quality of nanocrystals and the electrical properties of boundary layers between them. We investigated the use of radio frequency sputtering, atomic layer deposition, and pulsed laser deposition techniques to fabricate self-assembled nanocrystalline thin films and determined the influence of deposition conditions on the performance of transistors. Device design and fabrication parameters were also optimized to demonstrate TFTs with high current density and high speed performance comparable to single crystalline-based transistors.

show abstract

“…Indeed, based on Table I, when pinning is considered at 200 mV above midgap, the summation of simulated individual contributions (σV T ≈ 62 mV at V ds of 50 mV, and σV T ≈ 67 mV at V ds of 1.1 V) becomes pretty close to the measured variability. Following [9], this Fermi-level pinning indicates a trap density equal to 1.5 * 10 14 /cm 2 , which is a realistic value [15], [16].…”

Section: Resultsmentioning

confidence: 99%

Quantitative Evaluation of Statistical Variability Sources in a 45-nm Technological Node LP N-MOSFET

Cathignol

Cheng

Chanemougame

et al. 2008

IEEE Electron Device Lett.

View full text Add to dashboard Cite

Abstract-A quantitative evaluation of the contributions of different sources of statistical variability, including the contribution from the polysilicon gate, is provided for a low-power bulk N-MOSFET corresponding to the 45-nm technology generation. This is based on a joint study including both experimental measurements and "atomistic" simulations on the same fully calibrated device. The position of the Fermi-level pinning in the polysilicon bandgap that takes place along grain boundaries was evaluated, and polysilicon-gate-granularity contribution was compared to the contributions of other variability sources. The simulation results indicate that random discrete dopants are still the dominant intrinsic source of statistical variability, while the role of polysilicon-gate granularity is highly dependent on Fermilevel pinning position and, consequently, on the structure of the polysilicon-gate material and its deposition and annealing conditions.

show abstract

Modeling of laser-annealed polysilicon TFT characteristics

Cited by 63 publications

References 12 publications

Dependence of polycrystalline silicon thin-film transistor characteristics on the grain-boundary location

Dependence of polycrystalline silicon thin-film transistor characteristics on the grain-boundary location

Self-assembled nanocrystalline ZnO thin film transistor performance optimization for high speed applications

Quantitative Evaluation of Statistical Variability Sources in a 45-nm Technological Node LP N-MOSFET

Contact Info

Product

Resources

About