In this paper, an analytical drain current model of double gate MoS2 FET Transistor for low‐frequency noise (LFN) power spectral density is developed, and compared its response with the device simulation of the proposed device structure. The developed low‐frequency noise power spectral density (PSD) model is analyzed with respect to different Trap densities, Oxide thicknesses, and high K‐dielectric materials using the TCAD Device simulation tool. Low‐frequency noise is one of the most important noises in any device since it degrades the device's performance. So, in this paper, we used a unique charge‐control model for analyzing the low‐frequency noise by considering the mobility degradation, trapping, and de‐trapping effects caused by trap densities and device lattice structure. Usually, all the previous studies on drain currents with low frequency are based on fluctuations caused by mobility and carrier variations. In our paper, we even considered the charge density fluctuation to analyze the drain current equation. Using a Charge Control Model, we can compute the parameters like gate capacitance (Cgs, Cgd), channel length modulation, and body effect. While other LFN models like the DC model, small signal model, and hybrid model will focus mainly on the static characteristics of the device such as its DC current–voltage (I‐V) relationship, terminal resistances, and input/output conductance of the devices. All the analytical model results were calibrated with the device simulation and it is observed that both are matches each other. Further, it is observed that with an increase in Trap density, the low‐frequency noise increases and low‐frequency noise is dominant at lower frequencies only (1–10 Hz), and after this frequency range the thermal noise will be the dominant noise factor.