Modeling optimization of test patterns used in de-embedding method for through silicon via (TSV) measurement in silicon interposer

Wang, Qian; Erickson, Nicholas; Cho, Jonghyun; Hwang, Chulsoon; Fan, Jun; Paulis, Francesco de; Piersanti, Stefano; Orlandi, Antonio; Achkir, Brice

doi:10.1109/isemc.2016.7571683

Cited by 7 publications

(2 citation statements)

References 8 publications

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“…Chip-package-system board integrated simulation can provide analytical insights of internal states once models are properly prepared for electronic components including IC chips [19]- [21]. Packaging materials are electrically characterized for modeling passive impedance [22], [23]. The simulation concatenates the passive models and active circuits to solve dynamic behaviors of powering and signaling.…”

Section: Introductionmentioning

confidence: 99%

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging

Sonoda

Kasai

Tanaka

et al. 2022

IEEE Trans. Compon., Packag. Manufact. Technol.

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This article confirms the advantage of fan-out (FO) packaging in the electrical performance of power delivery among integrated circuit (IC) chips with the best use of land side capacitors (LSCs). On-chip in-place waveform measurements quantitatively evaluate the integrity of powering and signaling within FO wafer level packaging (FOWLP) multiple chip module (MCM) demonstrators, where a pair of IC chips are assembled with LSCs with different sizes and structures. The IC chip incorporates an array of 12 digital cores and on-chip waveform monitor (OCM) circuits. Each digital core consists of a low-voltage differential signaling (LVDS) transceiver channel that is backed by a static random access memory (SRAM)-based builtin self test (BIST) module and supplied by an on-chip voltage regulator module (VRM). The LSCs are placed on the bottom side of an FO interposer and inserted between the output of VRM and the ground plane almost ideally with the shortest length of physical traces. A Si membrane capacitor of 10 nF sustains the lowest power line impedance over the frequency range of 2.0 GHz more constantly than a multilayer ceramic counterpart, and attenuates the high-order harmonic frequency components to the clocking frequency at 750 MHz. The leverage of LSCs in powering also improves signaling and helps achieve the wider eye openings in LVDS channels. The implications are elaborated for the capacitor selections with respect to the physical types of capacitors, the size of capacitances, and the level of shares in power delivery among digital cores, all toward the higher level of integrity in powering and signaling in FOWLP MCMs.

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Section: Introductionmentioning

confidence: 99%

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging

Sonoda

Kasai

Tanaka

et al. 2022

IEEE Trans. Compon., Packag. Manufact. Technol.

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“…Then, some potential sources of error are hypothesized and overcome by proposing solutions based on a de‐embedding plane that can ensure a TEM (or quasi‐TEM) mode propagation 6,7 . In particular, in reference 8, the electrical performance of the test patterns used in the de‐embedding method for DUT characterization was studied thoroughly and for all test patterns, and full wave models were built and then analyzed based on simulated electrical performances. About analytical methods, Chen 9 has shown that the de‐embedding procedures are sensitive to manufacturing variations in the test fixtures, as well as inaccuracies associated with the calibration and measurement process.…”

Section: Introductionmentioning

confidence: 99%

Generalized analytical formulation for de‐embedding of multiport devices based on known fixtures

Scafati

Paulis

Olivieri

et al. 2022

Int J RF Mic Comp-Aid Eng

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The de-embedding is a technique used in radio frequency and signal integrity measurements to extract the scattering (S)-parameters of the device under test (DUT) from the measured data of a global assembly and based on known S-parameters of the left and right test fixtures; thus, it removes the impact of the text fixtures used for the connection of the DUT to the instrumentation. Once the S-parameters are measured, the de-embedding is performed by a multistep approach involving the bidirectional transformation of the S-parameters into the corresponding transfer scattering (T)-parameters. The latter approach is well established for two-and four-port networks and has been recently expanded to the multiport case. This work proposes an alternative analytical formulation to de-embed a multiport device, knowing in advance only the S-parameters of the global multiport assembly and those of the test fixtures. The proposed method does not involve the S-to-T conversion and it requires only the algebraic manipulation of the S-parameter matrix elements; its practical implementation is very well fitted especially for multiport cases, and it is very fast in calculating the de-embedded DUT S-parameters for large port numbers. The results of the proposed formulation, applied to the case of a multipin high-speed connector, are compared with those obtained by measurement and simulations.Their accuracy is shown and discussed to demonstrate the validity of the proposed approach.

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Crosstalk of octagonal TSV array arrangement based on differential signal

Han

Liu

Zhu

et al. 2021

2021 5th IEEE Electron Devices Technology &Amp; Manufacturing Conference (EDTM)

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Modeling optimization of test patterns used in de-embedding method for through silicon via (TSV) measurement in silicon interposer

Cited by 7 publications

References 8 publications

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging

Generalized analytical formulation for de‐embedding of multiport devices based on known fixtures

Crosstalk of octagonal TSV array arrangement based on differential signal

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