Modeling repeaters explicitly within analytical placement

Saxena, Prashant; Halpin, Bill

doi:10.1145/996566.996759

Cited by 14 publications

(14 citation statements)

References 13 publications

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“…Using interconnect delays instead of lengths has been a challenge, as wires can be dynamically re-buffered when their lengths change [15]. Unlike much of past literature, we use a buffered delay model to account for this.…”

Section: B Register Retimingmentioning

confidence: 99%

SPIRE: A retiming-based physical-synthesis transformation system

Papa¹,

Krishnaswamy²

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-The impact of physical synthesis on design performance is increasing as process technology scales. Current physical synthesis flows generally perform a series of individual netlist transformations based on local timing conditions. However, such optimizations lack sufficient perspective or scope to achieve timing closure in many cases. To address these issues, we develop an integrated transformation system that performs multiple optimizations simultaneously on larger design partitions than existing approaches. Our system, SPIRE, combines physically-aware register retiming, along with a novel form of cloning and register placement. SPIRE also incorporates a placement-dependent static timing analyzer (STA) with a delay model that accounts for buffering and is suitable for physical synthesis. Empirical results on 45nm microprocessor designs show 8% improvement in worstcase slack and 69% improvement in total negative slack after an industrial physical synthesis flow was already completed.

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Section: B Register Retimingmentioning

confidence: 99%

SPIRE: A retiming-based physical-synthesis transformation system

Papa¹,

Krishnaswamy²

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…For the short wires, lower metal layers are utilized, since reliability and resistance of the vias along with subsequent congestion does not justify the use of upper metal layers. The range of wirelengths and choice of metal layers can be determined empirically for a given process technology as in [24], and this can be used to compute wire-delays during technology mapping. We employ such a scheme to account for the wire-loads and delays during congestion-aware delay-oriented mapping.…”

Section: Congestion-aware Delay-oriented Mappingmentioning

confidence: 99%

A predictive distributed congestion metric with application to technology mapping

Shelar

Sapatnekar

Saxena

et al. 2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Due to increasing design complexities, routing congestion has become a critical problem in VLSI designs. This paper introduces a distributed metric to predict routing congestion and applies it to technology mapping that targets area and delay optimization. Our technology mapping algorithms are guided by a probabilistic congestion map for the subject graph to identify the congested regions, where congestion-optimal matches are favored. Experimental results on a set of benchmark circuits in a 90 nm technology show that congestion-aware mapping results in a reduction of 37%, on an average, in track overflows with marginal gate-area penalty as compared to conventional areaoriented technology mapping. For delay-oriented mapping, our algorithm improves track overflows by 20%, on an average, in addition to preserving or improving the delay, as compared to the conventional method.

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“…We use net weighting in a completely novel way, viz., to nudge nets away from repeater insertion and towards deletion thresholds. In this paper, we modify industrial implementations of the Kraftwerk global placer [10] that incorporates native repeater modeling [11], as well as the force-directed-Mongrel (FD-Mongrel) coarse legalizer [12] [13], in order to investigate the effects of net weighting on repeater count reduction during placement.…”

Section: Introductionmentioning

confidence: 99%

Net weighting to reduce repeater counts during placement

Goplen

Saxena

Sapatnekar

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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We demonstrate how to use placement to ameliorate the predicted repeater explosion problem caused by poor interconnect scaling. We achieve repeater count reduction by dynamically modifying net weights in a context-sensitive manner during global placement and coarse legalization. Our scheme, which models layer assignment as well as valid inter-repeater distance ranges, can decrease the repeater counts significantly with minimal impact on wirelength.

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Modeling repeaters explicitly within analytical placement

Cited by 14 publications

References 13 publications

SPIRE: A retiming-based physical-synthesis transformation system

SPIRE: A retiming-based physical-synthesis transformation system

A predictive distributed congestion metric with application to technology mapping

Net weighting to reduce repeater counts during placement

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