Modeling routing demand for early-stage FPGA architecture development

Abstract

Architecture development for FPGAs has typically been a very empirical discipline, requiring the synthesis of benchmark circuits into candidate architectures. This is difficult to do in the early stages of architecture development, however, because there is no complete architecture to synthesize circuits into. The effort required to create prototype tools for nascent architectures is far too great for every new logic block or routing architecture idea, and so it would be extremely helpful to have a simple and intuitive FPGA interconnect model to guide the architect.In this paper we present such an interconnect model for island-style FPGAs, whose single output is the estimated routing demand (often referred to as W, the number of routing tracks per channel) for an FPGA as a function of several logic block, circuit and routing architecture parameters. The goal of this model is to be as simple as possible, while still accurate enough to be useful, to provide understanding and intuition on FPGA routing. Our methodology is empirical -we propose model forms based on empirical observations, intuition and some derivation, and then fit models to experimentally generated data.We show the development of the model in stages, beginning with a fully flexible FPGA, and gradually proceeding to one which includes the key parameters that control the flexibility of FPGA routing, and one key parameter describing the logic block and another relating to the typical circuit. We then show how to use these models in early-stage architecture development to provide feedback on several aspects of logic block architecture. We also show how the model can be used to explore the routing architecture space itself and to provide an overall intuition for architecture development.

Area estimation and optimisation of FPGA routing fabrics

“…Routing area models have also seen significant advancement over the past few years. In [3], a set of equations was developed that describes the number of programmable routing tracks necessary in homogeneous FPGA architectures depending on a number of parameters that describe the routing architecture. The work assumed all benchmark circuits have a constant wirelength, regardless of the FPGA architetcure parameters.…”

“…To estimate the channel width of the device, we employ the model developed in [3]. This model is shown in (1) for architectures with wires that span one logic block, where the nominal minimum channel width W min is described by (2), and β, α in , α out are empirically derived constants.…”

“…Recently, a number of research publications have appeared that advocate the use of some form of analytical model to determine FPGA architecture parameters [1,2,3,4,5]. The main contribution of [2,3,4] has been to demonstrate that equation-based high-level models can relatively accurately capture some of the design trade-offs present in FPGA architectures, without resorting to computationally intensive empirical methods based on tools such as VPR [6].…”

“…The main contribution of [2,3,4] has been to demonstrate that equation-based high-level models can relatively accurately capture some of the design trade-offs present in FPGA architectures, without resorting to computationally intensive empirical methods based on tools such as VPR [6]. Such an ability becomes increasingly important as the number of parameters that define an FPGA architecture increases (e.g.…”

“…The proposed approach combines the model of [3] for channel width with a simple model of the impact of logic block size, input and output connection box flexibility and channel width on FPGA routing area. The intuition is that reduced routing flexibility reduces the area of the multiplexers associated with connection and switch boxes, but at the same time exerts pressure on increased channel width.…”