Modeling, Simulation and Optimization of 14nm High-K/Metal Gate NMOS with Taguchi Method

Mah, S. K.; Ahmad, Ibrahim; Ker, Pin Jern; Tan, K.P.; Faizah, Z. A. Noor

doi:10.1109/smelec.2018.8481293

Cited by 2 publications

(2 citation statements)

References 7 publications

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“…To solve the issue of excessive IOFF, it is being explored to introduce high-k dielectric materials as one of the gate oxide management solutions. Additionally, a high-k dielectric can be used to achieve a larger gate capacitance at a greater thickness [16], [17].…”

Section: Introductionmentioning

confidence: 99%

“…Since WSix is compatible with both negative channel metal oxide semiconductor (NMOS) and positive channel metal oxide semiconductor (PMOS) devices, the metal-gate work-function engineering patent facilitates its usage as a metal gate. WSix is believed to have a variety of applications and strong thermal stability and conductivity [17], [22].…”

Section: Introductionmentioning

confidence: 99%

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Optimization of 14 nm double gate Bi-GFET for lower leakage current

Nizam

Hamid²,

Salehuddin³

et al. 2023

TELKOMNIKA

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In recent years, breakthroughs in electronics technology have upgraded the physical properties of the metal oxide semiconductor field effect transistor (MOSFET) toward smaller sizes and improvements in both quality and performance. Hence, the growth field effect transistor (GFET) is being promoted as one of the worthy candidates due to its superior material characteristics. A 14 nm horizontal double-gate bilayer graphene field effect transistor (FET) utilizing high-k and a metal gate, which are composed of hafnium dioxide (HfO2) and tungsten silicide (WSix) respectively. Silvaco ATHENA and ATLAS technology computer-aided design (TCAD) tools are used to simulate the design and electrical properties, while Taguchi L9 orthogonal arrays (OA) are used to optimize the electrical properties. The threshold voltage (VTH) adjustment implant dose, VTH adjustment implant energy, source/drain (S/D) implant dose, and S/D implant energy have all been investigated as process parameters, while the VTH adjustment tilt angle and the S/D implant tilt angle have been investigated as noise factors. When compared to the initial findings before optimization, the IOFF has a value of 29.579 nA/µm, indicating a significant improvement. Findings from the optimization technique demonstrate excellent device performance with an IOFF of 28.564 nA/µm, which is closer to the international technology roadmap for semiconductors (ITRS) 2013 target.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%