Modeling Single Event Transients in Advanced Devices and ICs

Abstract

The ability for Single Event Transients (SETs) to induce soft errors in Integrated Circuits (ICs) was predicted for the first time by Wallmark and Marcus in the early 60's [1] and was confirmed to be a serious issue thirty years later. In the 90's microelectronic technologies reached the "deep submicron" era, allowing high density ICs working at frequencies faster than hundreds of MHz. This new paradigm changed the status of SETs to become a major source of reliability losses. Huge efforts have thus been made to characterize SETs in microelectronics, either using experiments or by simulation, in order to reveal key factors leading to SET occurrence, propagation and capture in modern ICs. In this context, modeling and simulation are of primary importance to get accurate SET predictions. This paper focuses on modeling SETs in innovative electronic devices which involves modeling steps at different scales, from ionizing particle to circuit response. After a brief review of the state-of-the art of modeling at each scale, this paper will discuss current capabilities and intrinsic limitations of SET modeling, the incoming challenges in advanced devices and ICs, and finally the methodologies to improve SET simulation and prediction for future technologies.

Circuit Techniques using Substrate Bias for Design of Radiation Hardened Voltage Controlled Oscillator

“…This paper shows the structural CMOS with and without radiation, and variation of electrical properties of device under various radiations doses and proposes a modified CMOS circuit that mitigates radiation effect by improving switch point in I-V characteristic. To redesign the circuit for radiation resistance; the radiation hardened inverter circuit is implemented in each stage of Voltage Controlled Oscillator (VCO) design [4], [5].…”

Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

“…In this sense, Monte Carlo simulation tools have solid foundations to be used in the study of radiation effects on electronics [9]. There are many works in the literature which propose the research of radiation effects on electronics exploiting simulations and avoiding the time consuming and expensive radiation campaigns [10][11][12][13][14][15][16][17]. Mixed-mode Technology Computer-Aided Design (TCAD) simulations have been vastly used to understand the main mechanisms in SEEs on electronics.…”

A Novel Radiation Hardened Parallel IO Port for Highly Reliable Digital IC Design

“…The phenomena of an unwanted upset of 1 to 0 or 0 to 1 in a memory cell such as an SRAM cell, level sensitive latch or flip-flop (generally sequential logic) caused by an energetic particle strike is called single event upset (SEU) [1][2][3]. Particle strikes could incur an unwanted glitch (a voltage pulse) in the combinational logic that is called single event transient (SET) [4][5][6][7].…”

“…To combat with the aforementioned soft errors, various techniques in all levels of abstraction are suggested [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15]. One costbenefit technique for improving the robustness of digital circuits against soft errors is radiation hardening by design [1,3,[7][8][9][10].…”

“…As can be found in the figure, there are two latches including one for storing the logic value that is for being written to IO pad and the other for the logic data value read from the pad. As discussed in [1][2][3][4][5][6], generally latches are prone to be affected by energetic particle strikes dramatically. Furthermore, the SETs came from combinational parts of the circuit.…”