Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits

KITO tool: A fault injection environment in Linux kernel data structures

“…An example of a model for fault injection analysis is presented in [20], where a library was created to predict single error rates in combinational circuits, considering typical current responses which depend on different characteristics of soft errors. In [15] a tool called MODIFI (MODel-implemented Fault Injection) is presented.…”

Systematic analyses for latching probability of single-event transients

“…Some logic gates, such as NAND and NOR gates, have a capability to tolerate errors from previous gates, which is explained in Section I. For logic network with logical masking, soft error rate is the product of the probability of no logical masking and the probability of SET being in latch window, as expressed in (16). SER  P no_logical_masking *P in_latching_window (16) Every logic gate has its special P no_logical_masking .…”

“…SPICE/HSPICE simulations [15,16] have indicated that the probability of latching window masking tightly depends on the SET pulse width and SET injection timing with respect to the flip-flop sampling moment. To reduce simulation time, previous work [13] tried to identify the critical SET pulse width in benchmark circuits and computation units.…”

Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits

“…Several methods that incorporate the various masking factors have been proposed to model and evaluate SER, such as the SEUTool (Massengill et al, 2000), the SERA tool (Zhang and Wang, 2006), the SEAT tool (Ramanarayanan et al, 2009) …”

“…Ramanarayanan et al (Ramanarayanan et al, 2009) model the three common masking effects (logical, electrical, latch-window) concurrently by: (1) capturing the current-voltage transfer characteristics for multiple current pulses at the input nodes, (2) accumulating the delay information for logic cells, (3) estimating the timing window for flip-flops by sweeping a voltage pulse of a specific width and height at the input of the flip-flop using HSPICE simulation, and (4) modeling the voltage glitch propagation using the mathematical equations proposed in the work. This tool is useful in terms of calculating the masking effects concurrently and efficiently.…”