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A multi-mode Secure Hashing Algorithm (SHA) accelerator is fabricated in 45nm CMOS and occupies 0.0625mm 2 with 18Gbps throughput and total power consumption of 50mW. The reconfigurable hardware accelerator computes SHA-1/224/256/384/512 message-digest using unified SHA bit-slices and configurable compression circuits resulting in 40% area reduction and <3% performance overhead for reconfiguration with 23Gbps peak throughput in SHA-224/256 modes. SHA frequency ranges from 21MHz-1.8GHz across 320mV-1.35V supply voltage range. I. INTRODUCTIONHash functions are important cryptographic primitives used to generate digital fingerprints or signatures [1] in publickey encryption workloads and internet protocols, such as Internet Protocol Security (IPSEC), Message Authentication Codes (MAC) and Secure Sockets Layer (SSL) [2]. The Secure Hashing Algorithms (SHA) family of hashes provides a variety of digest sizes (160b-512b) with varying number of rounds for a variety of applications. While SHA-1 is the most popular hash in use today, the SHA-2 family of hashes (SHA-224/256/384/512) offers enhanced security in the form of higher pre-image and collision resistance at the cost of higher computational complexity. SHA workloads are among the most performance/power-critical workloads due to the iterative nature of hash computation and the high computational complexity of mapping the parallel 64b additions, bitwise rotations and one-way compression functions on a general-purpose microprocessor execution core.